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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Welcome to the "Exploring the Virtual Platform" Series

Today I'm starting a series of articles related to what is commonly called the Virtual…

• 5 min read
virtual platform , System Design and Verification , virtual protoype

Verification

Aart DeGeus' Surprise Comment at Last Night's EDAC CEO Forum

Last night the Electronic Design Automation Consortium ("EDAC", the trade group for…

• 2 min read
IEEE 1647 , events , Functional Verification , e , EDAC

Verification

Generation Debugging With "IntelliGen" (With Video)

You might have seen the Generation Debugger of Specman's new Generation Engine IntelliGen…

• 3 min read
IntelliGen , Specman , e , Incisive Enterprise Simulator (IES) , IES

RF Engineering

MMSIM 7.1 Enhancements Benefit RF Designers!

The 7.1 release of MMSIM is scheduled for mid-January. There are many exciting RF…

• 2 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

System, PCB, & Package Design 

What's Good About Differential Pair Support in Allegro PCB Editor? More Features…

Some very helpful new features for Differential Pair support are available in in…

• 3 min read
SPB 16.2 , PCB design , Differential Pair Support , Allegro

Digital Design

Cool Way to Add Vias!

I knew this functionality existed, but I hadn't really put it to use until yesterday…

• 1 min read
SoC-Encounter , via , Digital Implementation , Add Via

Verification

Predictions for 2009

Having summarized the main verification technology-specific observations that the…

• 3 min read
Specman , HW/SW , verification strategy , metric driven verification (MDV) , Functional Verification , OSCI , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , SystemC , ISX , System Verification , Incisive Enterprise Simulator (IES) , IES

Verification

Functional Coverage for Embedded Software

Hardware verification has evolved into keeping track of a pile of different types…

• 3 min read
FoCus , IBM , System Design and Verification , Specmen , DV club

RF Engineering

Tip of the Week: Guidelines for getting accurate HB QPSS/QPNoise results

Two of the most important parameters for accuracy are: (1) maxharms (2) oversample…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design , Circuit Design

Verification

The New Generation Testcase Utility

Specman's new Generation Engine, "IntelliGen", adopts an entirely new generation…

• 4 min read
IntelliGen , Specman , Functional Verification , Testbench simulation , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

RF Engineering

How to Simulate a Subcircuit (Netlist) With Spectre in ADE

Many users ask, "How do I instantiate a netlist into my schematic and simulate with…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , Circuit Design

System, PCB, & Package Design 

What's Good About The SPB16.2 PCB SI Release? Full Wave Field Solver!

The SPB16.2 PCB SI release now contains the Electromagnetic Solution 2D Full Wave…

• 6 min read
PCB Layout and routing , SPB 16.2 , field solver , PCB design , Allegro PCB Editor , Allegro

Verification

A Look Back On 2008 (Before Hazarding Predictions for 2009)

Before I dare take a stab at adding to the many predictions already made for 2009…

• 4 min read
HW/SW , verification strategy , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , e , Enterprise Manager , Enterprise Planner , coverage driven verification (CDV)

Verification

The Eternal Debate: "Like" vs. "When" Inheritance

First: Happy New Year, Specmaniacs! Much like the rivarly between the New York Yankees…

• less than a min read
IEEE 1647 , Specman , verification strategy , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Digital Design

Coming This Friday January 9th: Encounter Digital Implementation Office Hours

Happy New Year everyone! I hope you all had a restful, enjoyable and healthy holiday…

• 1 min read
Digital Implementation forums , chat , Encounter Digital Implementation

Verification

Power tool: The Reflection API

One endless source of neat little tricks is the Reflection API built into Specman…

• 1 min read

Verification

Metric-Driven Verification in a Box...

In my last few posts, I was explaining our focus here in Cadence Verification on…

• 1 min read
metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Cadence VIP portfolio , OVM , VIP , Coverage-Driven Verification , CDV , e , Verification IP modeling , eRM

Verification

Make Your Command Line Life Easier With "specman -e"

Hi All, It always amazes me to see just how many Specman users make use of the interactive…

• 1 min read
Specman , Incisive Enterprise Simulator (IES) , IES

Verification

Who said Cadence Can't Invent New Technology Anymore?

I and the rest of the Cadence C-to-Silicon Compiler (CtoS) team were thrilled yesterday…

• 1 min read
deepchip , System Design and Verification , C-to-Silicon
CDNS - Fix Layout Hompage