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Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

SoC and IP

Android Audio Offload Explained at Mobile World Congress

Want to lower power in your next Android TM device? Look to the industry's first…

• less than a min read

Verification

New Incisive Verification App and Papers at DVCon by Marvell and TI

If you're an avid reader of Cadence press releases (and what self-respecting verification…

• 1 min read
Formal Analysis , formal , Funcional Verification , DVCon 2014 , Formal verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About DEHDL’s Cross Referencing of Hierarchical Nets? 16.6 has Several…

The 16.6 Design Entry HDL (DEHDL) Cross Referencer has some new enhancements to report…

• less than a min read
PCB , Cadence Design Systems , hierarchy , cadence , 16.6 , hierarchical schematics , SPB , Design Entry HDL , design , Design Entry , Grzenia , ConceptHDL , hierarchical block

Verification

Incisive vManager at DVCon - Come See It!

Have you heard the news? There is a new version of vManager announced this week,…

• 1 min read
collaboration , : Functional Verification , Verification methodology , cadence , Functional Verification , vPlan , Verisity , DVcon , metric-driven verification , functional coverage , vManager

Whiteboard Wednesdays

Whiteboard Wednesdays - How the MIPI Alliance Works to Enhance Mobile Devices

In this week's Whiteboard Wednesdays episode, Moshik Ruben, Product Marketing Director…

• less than a min read
mobile devices , UniPro , D-PHY , MIPI , MIPI protocols , M-PHY

Analog/Custom Design

What's the Worst that Could Happen?: Worst-Case Corners in ADE GXL

In addition to combinations of temperature range and power supply voltages (usually…

• 2 min read
Variability Aware Design , Corners analysis , worst case corners , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment

Whiteboard Wednesdays

Whiteboard Wednesdays - Implementing Always-On Audio

In this week’s Whiteboard Wednesdays episode, Gerard Andrews, from the Tensilica…

• less than a min read
mobile devices , Whiteboard Wednesdays , IP , sensor fusion , voice trigger , Tensilica , HiFi DSP , always on audio , audio playback

Analog/Custom Design

What Your Circuit Doesn't Know, Can Kill It!

Device variation has been a long-standing problem in custom design. Over the years…

• 1 min read
IP , post-extraction , corner , in-design , Virtuoso Analog Design Environment , physical implementation , device variation , IC design

System, PCB, & Package Design 

Improve Design Quality with Adjacent Layer Object Avoidance in the 16.6 Cadence APD…

In this week's discussion, let's take a look at a cornerstone of every good substrate…

• 2 min read
IC Packaging and SiP Design , package , packaging , IC Packaging and SiP , APD , IC Packaging & SiP design , SiP Layout , IC Package Physical layout and co-design

Verification

e Language Editing with Emacs

Specman and e have been around for a while, and some clever people have developed…

• 1 min read
AF , Specman , Incisive Debug Analyzer , e code , xemacs , Funcional Verification , editing , emacs

Whiteboard Wednesdays

Whiteboard Wednesdays - What is VIP?

Today, our continuing Whiteboard Wednesdays video blog series will provide an overview…

• less than a min read
Verification IP , Memory , VIP , EDA , interfaces , SoC design

System, PCB, & Package Design 

What's Good About Allegro/OrCAD/Sigrity Quarterly Incremental Releases (QiRs)? Check…

You’ve no doubt seen announcements (either via customer emails, on the Cadence website…

• 1 min read
PCB , Allegro 16.6 , 16.6 , Support , SPB , Front-end PCB design , OrCAD , Sigrity , Allegro

Verification

Incisive Verification: Top 10 Things I Learned While Browsing Cadence Online Support…

There is always a demand, in most corners of the world today, for learning and troubleshooting…

• 9 min read
IEEE-1801 , LPS , App Note Incisive Simulation , Cadence Online Support , RAK , UVC , UPF , IES

SoC and IP

My Love-Hate Relationship with Mobile World Congress

My friends are jealous. I get an all-expense-paid trip to Barcelona, Spain to see…

• 1 min read
Design IP , MIPI , Mobile World Congress , MWC , Tensilica

Whiteboard Wednesdays

Whiteboard Wednesdays—Imaging, Video, and Embedded Vision

Today, our continuing Whiteboard Wednesdays video blog series will shed some light…

• less than a min read
Design IP , Whiteboard Wednesdays , IP , video , embedded vision , Tensilica , imaging , imaging video

Verification

Cadence and AMD Add New UVM Multi-Language Features

The UVM Multi-Language Open Architecture open-source library was recently updated…

• 2 min read
IEEE 1647 , SystemVerilog , uvm , IEEE 1800 , UVM-ML , VCs , Incisive , e , IEEE 1666 , Accellera , SystemC , Questa , IES-XL

SoC and IP

Latest Developments in Ethernet Standards

Cadence is committed to supplying Ethernet silicon and verification IP to help its…

• 3 min read
Ethernet standards , IEEE 802.3 , Ethernet , Marris , 802.3bj

System, PCB, & Package Design 

What's Good About Allegro PCB Editor CM Analysis Control? 16.6 Has a Few New Enhancements

Beginning with the 16.6 version of Allegro PCB Editor , you can now toggle the Analysis…

• less than a min read
PCB , constraints manager , Cadence Design Systems , Constraint-driven PCB Design flow , data management , constraint databases , Allegro GUI , Allegro 16.6 , cadence , 16.6 , SPB , PCB Editor , Constraint Manager , PCB routing , design , PCB design , Constraints , Grzenia , Allegro PCB Editor , Constraint Driven PCB routing , PCB Capture , Allegro

Verification

Covering Edges (part II)—“Inverse Normal” Distribution

In the previous example , we used the "select edge" to generate edge values for fields…

• less than a min read
AF , e language , Funcional Verification , functional coverage , coverage driven verification (CDV) , Aspect Oriented Programming
CDNS - Fix Layout Hompage