Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Tech Tip: Easy Way To Re-Run Using The Same Seed

[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week…

• 2 min read
Specman , Funcional Verification , IES-XL

System, PCB, & Package Design 

What's Good About DEHDL Font Support? The Secret's in The SPB16.3 Release!

Well - it's here! Native font support in Allegro Design Entry HDL (DEHDL)! This has…

• 8 min read
DEHDL , SPB 16.3 , Allegroro , PCB design , Design Entry , File Directives

SoC and IP

What’s on the Horizon for NAND and DRAM?

Young Choi , Guest Blog for Denali Software January is a time where lots of…

• 4 min read

Verification

What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology…

Cadence is in the vanguard of a movement to a higher level of productivity via the…

• 3 min read
TLM , RTL , System Design and Verification , IP re-use , Synthesis , verification

Digital Design

Three Reasons to Move to EDI System 9.1

We recently announced the 9.1 version of the Encounter Digital Implementation System…

• 1 min read
Foundation Flow Design Closure , Encounter Digital Implementation System 9.1 , Digital Implementation , EDI system Encounter Digital Implementation System

System, PCB, & Package Design 

Come See TeamAllegro at DesignCon2010

A new year means another DesignCon and 2010 is an exciting year for the PCB and IC…

• 1 min read
SiP , Signal Intregrity , Allegro 16.3 , IBIS-AMI , PCB design , Desigcon

Verification

How Big Is An int?

This week I'm taking a break from my series on Android System Verification to talk…

• 8 min read
Small Device C Compiler , wishbone , z80 , OpenCores , ISX

Verification

Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend…

• 1 min read
Functional Verification , CPF , Low-Power , UPF , SystemC , IES , ESL

Verification

A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made…

• 3 min read
SystemVerilog , metric driven verification (MDV) , Functional Verification , C , EDA , e , multi-language , coverage driven verification (CDV) , SystemC , MDV , ESL

System, PCB, & Package Design 

What's Good About SiP Layout ADRC? See For Yourself Using The SPB16.3 Release!

In the SPB16.3 release, the SiP Layout Assembly Design Rules Checker (ADRC) User…

• 16 min read
SiP , DRC , SPB 16.3 , ACSET , ADRC , PCB design

Verification

Why UVM Does Not Equal OVM Plus VMM

In the numerous tweets, blog posts, and online forum discussions on the upcoming…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Verification

Methodology Is Important But Language Matters - Part 1

Historical trends in languagesMany of us have traveled around the world, and while…

• 3 min read
Verification planning and management , TLM , virtual platform , System Design and Verification , ESL High Level Synthesis , OVM , ASIC/ASSP , ANSI-C , C-to-Silicon , virtual prototype , C program , OSCiI , TLM 2.0-driven design , planning and management , ESL

SoC and IP

The Evolving Enterprise SSD: Gartner’s Forecasts

By Steve Leibson for Denali Software The appearance of SSDs into the storage…

• 5 min read

SoC and IP

SSD Interfaces and Performance Effects

By Steve Leibson for Denali Software IDC ’s Research Director John Rydning…

• 4 min read

SoC and IP

SSD and HDD Economic Forecast: Analyst Jim Handy Speaks Out

By Steve Leibson for Denali Software If you’re waiting for solid-state drives…

• 3 min read

Verification

Scalability Made OVM The Ideal Choice For UVM

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted…

• 1 min read
performance , SystemVerilog , uvm , OVM ML , Functional Verification , OVM , e , Simulation acceleration , MDV

Analog/Custom Design

Things You Didn't Know About Virtuoso: Options? What Options?

Recently, I got involved in helping out a customer who had become frustrated using…

• 1 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , IC 6.1.4 , Custom IC Design

Verification

Q&A With Nick Heaton: Accelerating Verification Methodology and Tool Adoption

TeamMDV: Have you ever wondered why EDA Vendors don't make it easier for our customers…

• 5 min read
workshops , IPCM , methodology , Verification methodology , metric driven verification (MDV) , Functional Verification , Incisive , Enterprise Manager , Plan and metrics management , MDV

Verification

Tech Tip: Waving Specman Objects in SimVision

Did you know that you can wave Specman objects in IES-XL *and* also save the wave…

• 1 min read
Specman , debug , Functional Verification , simvision , e , IES-XL
CDNS - Fix Layout Hompage