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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

中文技术专区

6G时代来了，我们应该为设计准备什么？

7月22日至23日，为期两天的“电子设计创新大会（EDICON China 2021）”在上海博雅酒店成功举行，本次大会汇聚了业界一众技术专家与企业领袖，与大家共同探讨最前沿的技术与最新行业发展趋势…

• less than a min read
5G , awr , RF design , Sigrity , Allegro , 6G , clarity

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment V16 ソフトウェアのリリースをハイライト

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• less than a min read
microwave , RF Simulation , Circuit simulation , Analyst 3D FEM EM Simulator , RF design , AXIEM 3D Planar Simulator , japanese blog , awr v16 , AWR Design Environment release , Visual System Simulator(VSS)

Breakfast Bytes

Sunday Brunch Video for 25th July 2021

https://youtu.be/cwT7KL4iShY Made on "a tropical beach" Monday: Aerospace and Defense…

• less than a min read
sunday brunch

RF Engineering

μWaveRiders: Cadence AWR Design Environment V16 Software Release Highlights

The Cadence AWR Design Environment V16 production release is now available for download…

• 3 min read
RF Simulation , Circuit simulation , Analyst 3D FEM EM Simulator , RF design , AXIEM 3D Planar Simulator , microwave office , Visual System Simulator (VSS) , awr v16 , AWR Design Environment release

Computational Fluid Dynamics

This Week in CFD

Given that I'm perpetually late on sharing This Week in CFD here on the Cadence CFD…

• less than a min read
CFD , Marine Engineering , Pointwise , Computational Fluid Dynamics , fluid dynamics , Omnis

System, PCB, & Package Design 

BoardSurfers: Accelerating Allegro Layout Tools Using NVIDIA GPUs for Complex Board…

Boards and Packages are getting extremely complex and large; what used to be considered…

• 1 min read
Allegro Package Designer , Allegro PCB Editor

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Download Manager – Better than Ever Before

The Download Manager user interface has been revamped in 17.4-2019 HotFix 019. Various…

• 3 min read
Cadence Design Systems , Installation Know-How , 17.4 , BoardSurfers , Allegro OrCAD Installer , 17.4-2019 , Download Manager , OrCAD , installation , Allegro

Computational Fluid Dynamics

Damen: Wind Study On A Slender Boat Design Using Computational Fluid Dynamics

DAMEN and Numeca develop a CFD methodology to proof a vessel has sufficient transversal…

• 1 min read
naval archicture , Marine Engineering , Wind Study , fluid dynamics , IMO regulations , simulation software

Breakfast Bytes

Machine Learning in EDA

Yesterday, in my post Cerebrus: The Future of Intelligent Chip Design , I talked…

• 5 min read
featured post , xcelium ml , cerebrus , JasperGold , allegro x

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.019 is Now Available

The HotFix 019 (QIR 3, indicated as 2021.1 in the application splash screens) update…

• 6 min read
System Capture , 17.4 , OrCAD Capture , PSPICE , PCB Editor , EDM , Allegro Package Designer , 17.4-2019 , Topology Explorer , Allegro System Capture , Allegro PCB Editor , Pulse , 17.4-QIR3

Breakfast Bytes

Cadence Cerebrus - Intelligent Chip Explorer

This morning, we announced the Cadence Cerebrus Intelligent Chip Explorer, a machine…

• 5 min read
Genus , featured post , cerebrus , cloud , cadence cloud , Innovus , digital full flow , physical design , Synthesis , timing signoff

Life at Cadence

How Culture Can Flourish in the New Normal

Peter Drucker rightly said, “Culture eats strategy for breakfast”. An inclusive high…

• 5 min read
Culture

Breakfast Bytes

CadenceLIVE Cloud Panel

At the recent CadenceLIVE Americas, most of the sessions were pre-recorded with a…

• 11 min read
featured post , on-prem , cloud , cadencelive americas , cadence cloud , cadencelive

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Cadence Learning and SupportポータルのVirtuoso RF Solutionプロダクト…

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• 1 min read
VRF , Virtuoso Meets Maxwell , COS product page , Virtuoso RF Solution , Spectre , japanese blog , Clarity 3D Solver , Cadence Learning and Support portal , Custom IC Design , VMM

カスタムIC／ミックスシグナル

Virtuoso Video Diary: LSCSジョブ制御モード - クラウド・シミュレーションを実現

Virtuoso ADE Assembler はアナログやミックスシグナルの設計のためシミュレーションを実行する、信頼されたツールとなっています。しかし、大量のシミュレーションを行うような状況では…

• less than a min read
cloud simulations , Virtuoso ICADVM20.1 , ADE Explorer , custom IC simulation , ADE XL , cloud , ADE , Virtuoso Analog Design Environment , Virtuoso Video Diary , Virtuoso IC6.1.8 , large-scale simulations , japanese blog , Custom IC Design , ADE Assembler

Verification

Comprehensive Approach to Verification of Interconnect-Centric Systems

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP…

• 2 min read
interconnect , scoreboard , SoC verification , Functional Verification

Analog/Custom Design

Virtuosity: Making Optimum Use of Resources in Distributed Farm

Details on a dedicated tab "Resources" in Job Policy form, which helps to do resource…

• 4 min read
SGE , Analog Design Environment , LBS , Job Policy , ADE , LSF , Virtuoso , Virtuosity , distributed processing , Custom IC Design , IC6.1.8 , Assembler , ADE Assembler

Breakfast Bytes

75 Years of the Microprocessor

At the recent ISCA, there was a panel session with some of the major contributors…

• 7 min read
isca , microprocessor

Verification

Why IDE Security Technology for PCIe and CXL?

The new cloud, AI, Analytics, and Edge usage models with exponential data growth…

• 3 min read
Verification IP , Functional Verification , VIP , System Verification , simulation , verification
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