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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Breakfast Bytes

Where You Going? Barcelona (and Mobile World Congress)

Mobile World Congress (MWC) is later this month in Barcelona in Spain (actually in…

• 3 min read
mwc16 , barcelona , Mobile World Congress , MWC , Tensilica , tensilican vision dsp , tensilica hifi , Breakfast Bytes

Breakfast Bytes

Autonomous Vehicles and the Semiconductor Industry: a Double-Edged Sword

A couple of weeks ago, I wrote about how automotive companies are going to need to…

• 3 min read
Automotive , sidecar , lyft , ADAS , autonomous vehicles , general motors

System, PCB, & Package Design 

How to Maximize Performance When Your Package Layout Gets Complicated

We are all familiar with it. Every year, designs get faster, smaller, and more complicated…

• 6 min read
Cadence Design Systems , SiP , Digital SiP design , IC package design , APD , package design , Allegro Package Designer

Breakfast Bytes

Datacenter in a Can

Earlier this week I wrote about the Linley Data Center Conference and how Thermal…

• 3 min read
microsoft , data center , google , thermal , cooling , power

Breakfast Bytes

"Thermal is the New Power" and Melting Butter with Your Phone

For some time now, SoC design groups have had to optimize PPA: performance, power…

• 4 min read
thermal management , PPA , thermal , power

Breakfast Bytes

Linley Data Center Conference: FPGAs and ARMs in the Cloud

Next week, February 9-10, is the Linley Data Center Conference in the Santa Clara…

• 4 min read
Altera , linley group , Linley , cloud , xilinx , ARM , datacenter , Breakfast Bytes , FPGA , cloud computing

Whiteboard Wednesdays

Whiteboard Wednesdays—Mapping Convolutional Neural Networks to the Vision P5 DSP

In this week's Whiteboard Wednesday, Chris Rowen explains how convolutional neural…

• less than a min read
Vision P5 , Whiteboard Wednesdays , IP , Chris Rowen , Computer Vision , Tensilica , convolutional neural networks , CNNs , image processing

Academic Network

Cadence Academic Network Sponsors Build 18, an Annual Freestyle Tinkering Festival…

What happens when you challenge a group of electrical and computer engineering students…

• 1 min read
build 18 , build , Cadence Academic Network , cmu , carnegie mellon univiersity

Breakfast Bytes

Modus Test Solution—Tests Great, Less Filling

Today Cadence announced the latest product in the "us" series of next-generation…

• 4 min read
modus test , low pincount test , modus , Test , codec , 2D elastic compression , test compression , Breakfast Bytes

System, PCB, & Package Design 

Cadence Online Support – Empowering Learning! New Learnings from December 2015

Documentation plays a significant role in helping to understand the software. Cadence…

• 5 min read
Cadence Online Support , IC package design , Cadence Help , Cadence Application Notes , RAKs , Allegro

Academic Network

How to Start as an IT Intern and Become a Cadence Employee

Here at Cadence we are very proud to provide internships to students and graduates…

• 2 min read
Interns , Cadence Academic Network

SoC and IP

DesignCon Demonstration of IP for PCIe 4.0 and 16Gbps Multi-Protocol PHY

We enjoyed sharing our latest news with the many people who visited our booth at…

• less than a min read
DesignCon , PCIe Gen4 , pcie4 , Design IP and Verification IP , SerDes

Breakfast Bytes

Conway's Law and the Changing Structure of Automobile Companies

There is a law in business organization known as Conway's Law. This states that:…

• 4 min read
Apple , organizational structure , google , tesla , automobile companies , conway's law

Breakfast Bytes

Moore's Law from 50,000 Feet

Moore's Law is in the news again since Intel, having maintained for years that nothing…

• 5 min read
semiconductor economics , ray kurzweil , moore's law , kurzweil , NASA , Breakfast Bytes

Academic Network

Education Weeks in Abu Dhabi

Abu Dhabi, the capitol of United Arab Emirates (UAE), has a vibrant academic scene…

• 2 min read
Cadence Academic Network , Abu Dhabi University , Virtuoso , microelectronics , university program

Breakfast Bytes

DesignCon: the 16Gbps Show

I always find DesignCon a slightly weird conference to attend. I swim in the semiconductor…

• 5 min read
DesignCon , 16gbps , PCIe 4 , designcon16 , measurement , Signal Integrity , SerDes , Sigrity

Whiteboard Wednesdays

Whiteboard Wednesdays—Key Metrics for Embedded Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , embedded neural networks

System, PCB, & Package Design 

What's Good About the Altium to Allegro PCB Editor Translator? It’s Now Available…

The current 16.6 HotFix now provides support for the Altium to Allegro PCB Editor…

• 2 min read
PCB , Allegro 16.6 , DEHDL , SPB , Design Entry HDL , PCB design , Grzenia , Allegro PCB Editor , Allegro

Breakfast Bytes

Misfit Shine 2 Lasts for 6 Months on a Coin Cell. How Do They Do That?

You can't go for very long without hearing about the Internet of Things (IoT) in…

• 3 min read
ClariTek , IoT , Misfit , Shine 2 , Breakfast Bytes , Patrick Mannion
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