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Corporate News

Spectre FX Simulator Cuts Intrinsic Semi’s Memory Verification Time by 4X

Intrinsic Semiconductor Technologies, a company transforming the semiconductor industry…

Corporate
• 2 min read
newstory , featured , spectre fx , Instrinsic Semi , verification

Corporate News

Cadence Welcomes ChipStack

ChipStack, a leading startup providing agentic AI solutions for chip verification…

Corporate
• 1 min read
featured , agentic ai , Xcelium Logic Simulator , AI-Driven Verification

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium
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Blog - Post List
Latest blogs

Breakfast Bytes

CES 2021: AMD, NVIDIA, and Mercedes

This is my second post about this year's CES. The first was Consumer Electronics…

• 7 min read
Consumer Electronics Show , CES , AMD , NVIDIA , Samsung , mercedes-benz

Life at Cadence

My Life at Cadence: Emmanuelle Amouriaux

We have recently interviewed some of our EMEA team members to hear about their unique…

• less than a min read
my life at cadence , cadence emea

Breakfast Bytes

Modus DFT Has Been ISO 26262 Certified by TÜV-SÜD

At the end of last year, Cadence's Modus DFT Software Solution was ISO 26262 certified…

• 5 min read
DFT , modus , tüv-süd , Test , ISO 26262 , certification

カスタムIC／ミックスシグナル

Virtuosity: Voltus-Fi-XLでのWhat-Ifメカニズムの解読

‘What if?’ は、仮想的なシナリオに有益な考えを誘導することを目的とした、小さいながらも強力な質問です。実際、それは私たちの想像力を飛躍させ、潜在的な出来事の理解を高め…

• less than a min read
EMIR Analysis , debug , Voltus-Fi-XL , what-if analysis , Virtuoso , Virtuosity , ICADVM20.1 , japanese blog , Custom IC Design , IC6.1.8 , EMIR

System, PCB, & Package Design 

BoardSurfers: Training Insights: Three Ways to Start OrbitIO System Planner

OrbitIO System Planner is a multi-fabric interconnect planning and optimization solution…

• 3 min read
17.4 , Cadence Online Support , OrbitIO System Planner , 17.4-2019

The India Circuit

Gowri Shankar: A Story of Overcoming Obstacles to Achieve Success

Shy and reticent Gowri Shankar is possibly the personification of the old saying…

• 1 min read
CadenceCares , CadenceScholarshipProgram , cadence

Breakfast Bytes

Cadence to Acquire Computational Fluid Dynamics Company NUMECA

This morning, Cadence announced that it was acquiring NUMECA International to expand…

• 2 min read
CFD , featured post , Computational Fluid Dynamics , NUMECA , Omnis

System, PCB, & Package Design 

IC Packagers: More Reasons to Move to 17.4 HotFix 013

As promised, we’re back with some more of the big improvements that are part of the…

• 4 min read
IC Packaging and SiP Design , 17.4 , Allegro Package Designer , 17.4-2019

Breakfast Bytes

Consumer Electronics Show 2021: GM, Intel

Normally, at this time of year I would be in Las Vegas, as I have been in January…

• 5 min read
Intel , Consumer Electronics Show , CES , general motors

カスタムIC／ミックスシグナル

Virtuosity: Conserve Power—パワーインテントのインポートとエクスポート

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso…

• less than a min read
Virtuoso Schematic Editor , virtuoso power manager , Conformal Low Power , VPM , Supply States , 1801 , setup , Virtuoso , Virtuosity , ICADVM20.1 , UPF , japanese blog , IEEE , mixed-signal design , Liberty , Custom IC Design , power domains

Breakfast Bytes

Sunday Brunch Video for 17th January 2021

https://youtu.be/mKoW8ji9_g8 Made in my kitchen (camera Ziyue Zhang) Monday: Young…

• less than a min read
sunday brunch

Breakfast Bytes

Offtopic: How to Make Spatchcock Chicken Under a Brick

It's Martin Luther King Day on Monday. Cadence is off. Breakfast Bytes will not appear…

• 3 min read
offtopic

RF /マイクロ波設計

2020年の日本語のCadence AWRソフトウェアに関するウェビナーコレクションを公開

AWRソフトウェアは、高周波設計のソリューションを紹介するために定期的にウェビナーを開催しています。次の2020年のウェビナーがAWRソフトウェアWebinarにまとめられました…

• less than a min read
RF , RF Simulation , AWR Design Environment , awr , RF design , japanese blog

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre Xの分散シミュレーションを使用したパフォーマンスと容量の向上

マルチスレッド/マルチコアシミュレーションのサポートは、長年にわたってSpectreで利用でき、ユーザーは、複数のコアを備えたひとつのマシンで、TRANやHBなどの単体の解析を実行できます…

• less than a min read
multithreaded simulation , ppn , Multi-Core , japanese blog , XDP , spectre x , Spectre X distributed simulation , multithreaded

Breakfast Bytes

Update: Achronix, SolarWinds, Wikipedia, US Fabs

This is another of my occasional update posts, where I revisit some older posts and…

• 10 min read
solarwinds , achronix , open source , darpa

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment V15.03 ソフトウェアのリリースをハイライト

Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence…

• less than a min read
RF , RF Simulation , AWR Analyst , Circuit simulation , AWR Design Environment , awr , Analog Simulation , AWR Design Environment V15.03 , AWR AXIEM , RF design , AXIEM 3D Planar Simulator , japanese blog , AWR Design Environment release

RF Engineering

μWaveRiders: Cadence AWR Design Environment V15.03 Software Release Highlights

The Cadence AWR Design Environment V15.03 production release with many enhancements…

• 2 min read
RF , RF Simulation , AWR Analyst , Circuit simulation , AWR Design Environment , Analog Simulation , AWR Design Environment V15.03 , AWR AXIEM , RF design , AXIEM 3D Planar Simulator , AWR Design Environment release

カスタムIC／ミックスシグナル

Virtuosity: DSPF Virtuoso EMIR解析フローのデビュー

読者のみなさん、こんにちは！ 設計エンジニアの生産性を継続的に改善することは、ケイデンスが従う戦略の中心であり、プロダクト全体でさまざまな革新と改善された機能をもたらしました…

• less than a min read
Voltus-Fi , EMIR Analysis , ADE Explorer , Voltus-Fi-XL , MMSIM , DSPF , EMIR Extraction , Spectre , Quantus Extraction Solution , Virtuosity , ICADVM20.1 , analog design , japanese blog , signoff , Custom IC Design , Virtuoso Layout Suite , simulation , IC6.1.8 , ADE Assembler

System, PCB, & Package Design 

BoardSurfers: How to Add Fanouts Using Standard Via Structures

An increase in design complexity has forced designers to take novel approaches to…

• 5 min read
17.4-QIR2 , 17.4-2019 , Allegro PCB Editor
CDNS - Fix Layout Hompage