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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Analog/Custom Design

Take Advantage of Advancements in Real Number Modeling and Simulation

Verification is the top challenge in mixed-signal design. Bringing analog and digital…

• 2 min read
real number modeling , analog , Mixed-Signal , RNM , mixed-signal verification

Verification

Xcelium and Cavium: What’s the Deal?

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers…

• 1 min read
thunder x2 , video , Cavium , xcelium

Breakfast Bytes

Patents: Licensed by the Ton

I wrote recently about What Happens in a Patent Lawsuit? Today, I want to look at…

• 8 min read
patent , troll , non-practising entity , cross-licensing , npe

SoC and IP

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

• 4 min read
Galileo , GPS , IoT , Tensilica DSPs

Breakfast Bytes

How Do You Get to Be CEO?

I wrote last week about Being CEO and I said that I'd done it twice in my career…

• 6 min read
board , management , chief executive officer , leadership , CEO

Analog/Custom Design

Virtuosity: New Eye Diagram Measurements

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create…

• 2 min read
Eye Mask , Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , ADE XL , ADE , eye diagram , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Verification

New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

As discussed in the previous installment of this blog, a new class of atomic transactions…

• 1 min read
amba5 , ACE5 , AXI5 , Atomic Transactions

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2018

https://youtu.be/wq86edcqTdw Coming from Building 10 lobby (camera Sean) Monday…

• less than a min read
fec , patent , journalism , Embedded World , forward error correction

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

Backchannel Training Another capability related to equalization adaptation is backchannel…

• 2 min read
Serial link analysis , IBIS-AMI , PCIe , Signal Integrity , Backchannel , Sigrity

Breakfast Bytes

Paul Kocher: Differential Power Analysis and Spectre

Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar…

• 11 min read
security , risc-v , Spectre , Paul Kocher , sifive

Digital Design

Wind of Change in Hardware Design

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I…

• 2 min read
High-Level Synthesis , deep learning , machine learning , Stratus , HLS

Breakfast Bytes

Is Big Brother Watching You?

I recently came across a fascinating piece by Paramal Satyal . He is Nepalese although…

• 6 min read
security , cookie , webbkoll , advertising

Verification

Coming to DVCon? It's Not Too Late to Sign Up!

Are you coming to DVCon this year? It’s right around the corner, but it’s not too…

• 1 min read
Functional Verification , DVcon 2018 , tutorials , event

Whiteboard Wednesdays

Whiteboard Wednesdays - Using DDR PHY Power Features to Reduce Power Dissipation

In this week's Whiteboard Wednesday video, Marc Greenberg explains the ways to optimize…

• less than a min read
Whiteboard Wednesdays , DDR PHY , Low Power DDR

Breakfast Bytes

embedded world 2018 Preview

It's nearly time for embedded world 2018 (yes, it likes to be trendy and put it all…

• 5 min read
Automotive , embedded world 2018 , 22fdx , Vision DSP , Tensilica , ADAS , GlobalFoundries

Breakfast Bytes

Why 1 Is Not a Prime Number

It's Presidents' Day and Cadence is on holiday. So time for me to write about something…

• 6 min read
PI , fundamental theorem of algebra , fundamental theorem of arithmetic , tau , central dogma of biology

Breakfast Bytes

Suddenly You Are CEO. What Do You Do Next?

We've covered sales , marketing , and application engineering . Let's go up to the…

• 7 min read
board , chief executive officer , CEO

Breakfast Bytes

What's For Breakfast? Video Preview February 19th to 23rd 2018

https://youtu.be/M3p1Luf4mtk Coming from Guangzhou, China (camera Carey Guo) Monday…

• less than a min read
cookie , Spectre , Paul Kocher , CEO , Embedded World , 3rd party cookie

Breakfast Bytes

Zombies

What is a zombie? It depends on who you ask. Venture capitalists talk about zombies…

• 8 min read
android , unix , iOS , zombie , linux , venture capital
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