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Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
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Blog - Post List

Latest blogs

Breakfast Bytes

Tensilica Floating Point: Small, Similar Cycles and Lower Power

When I first started programming, the first programming language I learned was Fortran…

• 6 min read
lx7 , DSP , fixed point , fortran , Linley , Tensilica , mathlab , floating point

Whiteboard Wednesdays

Whiteboard Wednesdays - How Much Floating Point Does Your Application Need?

To address the growing needs for floating-point arithmetic in DSP algorithms, all…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Tensilica , floating point

Analog/Custom Design

Virtuoso Video Diary: SPD – A Symbolic Way to Edit Your Physical Design

The best way to complete a complex task is to break it into smaller, simpler tasks…

• 5 min read
symbolic placement of devices , SPD , Virtuoso Video Diary

Breakfast Bytes

1,168 Reasons to Watch Training Bytes

Well, they told me that starting blog titles with a number is good clickbait. The…

• 2 min read
COS , self-learning , Cadence Online Support , training bytes

Verification

A Winning Strategy: Ethernet 10Base-T to Ethernet 400G!

Ethernet was developed in the 1970s and has been a viable communications protocol…

• 2 min read
Verification IP , 802.3bs , 25G Ethernet , VIP , Ethernet standards , IEEE 802.3 , Ethernet , future of IP , CHI VIP , Ethernet 400G

Breakfast Bytes

5nm: Do You Take the Red Pill or the Blue Pill?

I wrote recently about the TSMC OIP Symposium where they talked about future devices…

• 3 min read
tfet , 60 mV/decade , cnt , subthreshold sloope , carbon nanotube , Breakfast Bytes

Breakfast Bytes

How Can I Get Out of This House Without Going Anywhere Near Your Garage?

Go to any venture capitalist's website and they will have a bragging page with their…

• 2 min read
anti-portfolio , ebay , starbucks , bessemer.google , OVP , venture capital

Verification

What is ISO 26262 and Why Should I Care?

ISO 26262 is a functional safety standard applied to the development of electrical…

• 3 min read
Automotive , functional safety , cadence , ISO 26262

Breakfast Bytes

Linley Gwennap: Specialization Spurs Processor Innovation

Every year in the fall, the Linley Group runs their processor conference. There are…

• 5 min read
security , Intel , linley processor conference , AMD , x86 , IoT , Linley , ADAS , ARM , autonomous vehicles , power , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview October 3rd to 7th (video)

https://youtu.be/dv54rKmMLRo Monday: Options for 5nm. Silicon can only cut…

• less than a min read
60mV/decade , SystemVerilog , DSP , tensilica LX7 , CPF , Cadence videos , TSMC , parsers , Tensilica , training bytes , verific , n10 , 5nm , 10nm , ARM , floating point , VHDL , IEDM

Whiteboard Wednesdays

Whiteboard Wednesdays - Why Is More Floating-Point Computation Required by DSP Applications…

Why is more floating-point computation required by DSP applications? More and more…

• less than a min read
floating-point , DSP , Whiteboard Wednesdays , IP , communications processing , vision processing , Tensilica , wearables processing , floating point

Breakfast Bytes

Memories Are Made of This: Preview of MemCon

This year's MemCon is on October 11, at the Santa Clara Convention Center. Last year…

• 5 min read
vertical flash , Memory , LPDDR4 , MemCon , Micron , flash , NAND flash , Denali Party , DRAM , memcon 2016 , Breakfast Bytes

SoC and IP

3 Things You Didn't Know About MemCon 2016

Memcon is an event like few others, where SoC architects congregate to learn and…

• 1 min read
DDR4 , LPDDR4 , MemCon , DDR IP

Breakfast Bytes

TSMC: Technology Update

Twice a year TSMC has a big meeting in San Jose. These are the times that there is…

• 7 min read
OIP , 3D packagin , HPC28 , CoWoS , IoT , 28nm , 20nm , 40ULP , fabless , TSMC , ULP , process roadmap , 55ULP , 16ff , 16nm , InFO , 16FFC , n7 , FinFET , n10 , 7nm , 10nm , foundry

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Enhanced Backdrill Capability (Reason 4 of…

Adventures in Backdrilling For the past 15 years or so, routing high-speed interfaces…

• 4 min read
backdrill , Allegro 17.2 , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

System Design Enablement with Cadence and TSMC

System-on-chip (SoC) designers are always optimizing what has become known as PPA…

• 3 min read
Low Power , bvp.system-ppa , virtual platform , TSMC , Tensilica , power , Breakfast Bytes

Verification

Back in the Saddle Again

Nearly five years ago, I signed off with my last blog post in the Cadence Community…

• 3 min read
pswg , Perspec , System Design and Verification , System simulation and analysis , Accellera , portable stimulus , System Design and Verification , verification

Breakfast Bytes

Mellanox: Using Palladium ICA Mode

At CDNLive Israel, Yaron Netanel of Mellanox talked about his experience with Palladium…

• 3 min read
Yaron Netanel , CDNLive , debug , mellanox , Palladium , in-circuit acceleration , ICA , cdnlive israel , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview September 26th to 30th (video)

https://youtu.be/1le_bd4o01Q Monday: System Design Enablement with Cadence and…

• less than a min read
OIP , Memory , MemCon , LPDDR , liinley , SDE , TSMC , antiportfolio , DDR , system design enablement , bessemer ventures , power , microprocessor
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