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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

SoC and IP

Chris Rowen is Now an IEEE Fellow

For he's a jolly good Fellow, for he's a jolly good Fellow... Effective January…

• less than a min read
Chris Rowen , IEEE Fellow , Tensilica

Breakfast Bytes

Moore's Law at 50: Are We Planning for Retirement?

There has been lots of speculation, especially this year with the 50th anniversary…

• 5 min read
greg yeric , moore's law , ARM , IEDM

Whiteboard Wednesdays

Whiteboard Wednesdays—The Latest on the MIPI CSI-2 2.0 Protocol

In this week's Whiteboard Wednesdays video, Moshik Ruben takes a closer look at the…

• less than a min read
Automotive , CSI-2 , Low Power , Whiteboard Wednesdays , IoT , MIPI protocols , Internet of Things , bandwidth , machine vision

System, PCB, & Package Design 

What's Good About FSP’s Enhanced Multi-Device Connections? 16.6 Has Several New …

The FPGA System Planner (FSP) 16.6-2015 release now provides support for multiple…

• 1 min read
PCB , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , SPB , Grzenia , FPGA

Analog/Custom Design

Virtuosity: Things I Learned in October, November, and December 2015 by Reading Cadence…

I won't even attempt to number the items this time, and I'll have to skip the individual…

• 8 min read
EAD , Rapid Adoption Kit , ADE XL , VLS , RF design , Custom Layout , assertions , IC6.1.7 , Custom IC Design

Breakfast Bytes

Infrastructure: Connecting Mobile to the Cloud

Yesterday's blog post was about the mobile market. But, increasingly, mobile is not…

• 4 min read
computing , cloud-ran , c-ran , storage , infastructure , networking

Breakfast Bytes

I'm Goin' Mobile

"I'm goin mobile," The Who sang on one of the greatest albums of all time. Although…

• 3 min read
semiconductor IP , Internet of Things , mobile , system design enablement

SoC and IP

Word from the Source—USB-IF on USB Type-C Quality and Interoperability (Jeff Ravencraft…

In the first two parts of the interview with Jeff Ravencraft, the President and COO…

• less than a min read
USB 3.0 , cadence , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

SoC and IP

Word from the Source—USB-IF on USB Type-C and Alternate Modes (Jeff Ravencraft Interview…

If it wasn’t for the fact that USB has always been spelled with capital letters,…

• less than a min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Academic Network

Virtuoso Front-to-Back Workshop Series in Saudi Arabia

Starting Dec. 5 th , 11 PSATRI members attended a five-day workshop on the Cadence…

• 1 min read
Cadence Academic Network , Virtuoso , King Saud University , simulation

SoC and IP

Word from the Source—USB-IF on What USB-IF Is and What’s New in USB (Jeff Ravencraft…

In case you don’t know, USB Implementers Forum (USB-IF, for short) is the organization…

• less than a min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Breakfast Bytes

Nibbles—Breakfast Bytes Predictions for 2016

Neils Bohr, the physicist (or should that be the quantum mechanic) famously said…

• 3 min read
Automotive , predictions , USB Type-C , CES , SDE , design nodes , Test , 2016 , 3D packaging , system design enablement , Breakfast Bytes , Formal verification

Breakfast Bytes

Congratulations Chris Rowen, for He's a Jolly Good (IEEE) Fellow

So the lede is that Chris Rowen has been elected an IEEE Fellow. In a sense it is…

• 4 min read
Chris Rowen , IEEE Fellow , RISC processors , Tensilica , configurable processors

Whiteboard Wednesdays

Whiteboard Wednesdays - Understanding the Computational Activity Behind Neural N…

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the inter-workings…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , neural network , pattern recognition

System, PCB, & Package Design 

What's Good About ADW’s Component Browser for Project Manager? The Secret's in the…

The 16.6-2015 Allegro Design Workbench (ADW) release contains a significant enhancement…

• 1 min read
Allegro 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , component browser , design data management , PCB design , Grzenia , Librarians , library , ADW , Allegro

Breakfast Bytes

EDAC "Crossing the Chasm" with John Lee

EDAC's Emerging Companies Committee has been organizing evening seminars a couple…

• 6 min read
John Lee , EDAC , EDA standards , Jim Hogan , Ansys

Breakfast Bytes

IEDM: the International Electron Devices Meeting

IEDM is a meeting held annually since 1955. Historically, it has alternated between…

• 4 min read
International Electron Devices Meeting , IEDM , semiconductors , Breakfast Bytes

Breakfast Bytes

EUV Might Really Happen

I have been a skeptic about whether EUV was going to work. Just in case you have…

• 4 min read
lithography , 5nm test chip , defect , pellicle , 7nm , EUV , Breakfast Bytes

Academic Network

First Cadence Academic Network Workshop in Israel

On October 27, the Cadence Academic Network organized the 1st Cadence Academic Workshop…

• 1 min read
university , Cadence Academic Network , academic workshop , Bar Ilan University
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