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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good about the new "Class" Scope for Match Groups in Constraint Manager?

In the SPB16.01 release, for the Constraint Manager in DEHDL, the is a new scope…

• 1 min read
Constraint Manager , Class Scope , PCB design

Verification

System-level design and verification - at the center!

This year, Cadence increases its focus on system-level design and verification events…

• 1 min read
Acceleration , System Design and Verification , embedded software , Emulation , ESL handoff , System simulation and analysis , Coverage Driven Verification for Embedded Software , embedded SW engineer , CDNLive! Silicon Valley 2008 , ISX , Hardware/software co-verification , ESL , architect

Verification

Power Aware Design Now at System Level

Several years ago, I have purchased a cell phone with a 2 years contract from one…

• 2 min read
Acceleration , System Design and Verification , Low power verification and analysis , system validation/verification engineer , Verification Acceleration , System simulation and analysis , embedded SW engineer , Simulation acceleration , C-to-Silicon Compiler , Hardware/software co-verification , debugging , ESL , architect

Digital Design

Demo: Calling Global Timing Debug for a Single Path

Global Timing Debug has been a very popular capability within SoC-Encounter. Once…

• 1 min read
SoC-Encounter , STA , screencast , Digital Implementation , Global Timing Debug

Analog/Custom Design

Custom IC design, layouts, and productivity

There is a definite challenge in maintaining productivity when it comes to realizing…

• 1 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

System, PCB, & Package Design 

CDNLive! MVP discusses modeling 6 Gbps Serial Links with IBIS-AMI modeling

Congratulations to Donald Telian and his colleagues at Hitachi and IBM on winning…

• less than a min read
CDNLive! 2008 , PCB Signal and power integrity , IBIS-AMI , SPB , SPB16.2 , SerDes , CDNLive!

Verification

An informal introduction

Formal verification can mean different things depending upon who you speak to. If…

• 1 min read
Formal Analysis , Model-checking

System, PCB, & Package Design 

What's Good About Differential Pair Support in PCB Librarian?

You may recall a post I made a couple months ago about What's Good About Differential…

• 1 min read
DEHDL , Library and design data management , Design Entry HDL , Differential Pair Support , ConceptHDL

System, PCB, & Package Design 

CDNLive! - 10 Gbit package design paper available to conference attendees

For those of you that attended CDNLive! but may have missed the presentation on multi…

• less than a min read
PDN , CDNLive , 3D-IC , TSV , Allegro 16.2 , SPB , SPB16.2 , SerDes , SI analysis and modeling

Verification

Report from last week's "ClubT" events; preview of next week

As promised, here are some photos last week events, with embedded color commentary…

• 1 min read
SystemVerilog , HW/SW , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , multi-language , coverage driven verification (CDV) , ISX , eRM , System Verification , OVM 2.0 , IES

Digital Design

Interview: CDNLive! People’s Choice Winner Jason Gentry

At the recently completed CDN Live! Silicon Valley 2008 user conference, I had a…

• less than a min read
dbGet , robust data access , CDNLive! , "SoC-Encounter"

Analog/Custom Design

Custom IC design and design environments

Design environments have come quite a long way from the time I began my engineering…

• 1 min read
Virtuoso IC 6.1.3 , RF design , Custom IC Design , custom design technology

Verification

Users Take Over at CDNLive! 2008

This year I did not attend CDNLive! in San Jose. I wasn't presenting anything and…

• 2 min read
HW/SW , CDNLive San Jose 2008 , Functional Verification' signal integrity , ISX (Incisive Software Extensions)

Analog/Custom Design

Thanks Mr. Colton: Imitation really is the sincerest form of flattery

Recognize the name Charles Caleb Colton? No? He was a British writer who in 1820…

• 1 min read
Custom IC Design

Verification

The cell world

Earlier this Summer, I was lucky enough to attend the CDNLive show in Japan. One…

• 5 min read
IBM , Playstation , Toshiba , cell processor , Sony

System, PCB, & Package Design 

TSV, mainstream or niche?

I'm sure many of you will have read the article in Advanced Packaging click_here…

• 1 min read
Analog and RF SiP design , Digital SiP design , 3D-IC , IDMs , TSV , IC Packaging & SiP design , IC Package Physical layout and co-design

Analog/Custom Design

Latest Virtuoso news from CDNLive!

Hey Folks, thanks to all of you who participated in CDNLive SV. There was a lot of…

• 1 min read
CDNLive , Freescale , Virtuoso , Custom IC Design

Verification

In the EU next week for "ClubT" verification events

I'll be in the EU next week supporting "ClubT" events focused on advanced verification…

• 1 min read
SystemVerilog , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , Verification IP modeling , multi-language , coverage driven verification (CDV) , ISX , eRM , System Verification , OVM 2.0 , IES

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: A brief Re-cap

Wow - what a great time I had attending this year's CDNLive! 2008 event in San Jose…

• 2 min read
CDNLive! 2008 , PCB design
CDNS - Fix Layout Hompage