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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Digital Design

High-Level Synthesis: Why Now?

March 27, 2015 – With a title like “Why Now?”, you might expect this to be a sales…

• 2 min read
High-Level Synthesis , EDA , Forte , Stratus , HLS

Whiteboard Wednesdays

Whiteboard Wednesdays—The Power of WiGig (802.11ad)

In this week's Whiteboard Wednesdays video, Bob Salem explains WiGig (IEEE 802.11ad…

• less than a min read
wireless , Whiteboard Wednesdays , interfaces , 802.11ad , wiGig

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Highlight Nets Associated with Component? It…

With the 16.6 Allegro PCB Editor release, a simplified method to highlight or de…

• less than a min read
PCB Layout and routing , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor

SoC and IP

Link Training: Establishing Link Communication Between DisplayPort Source and Sink…

Link training is the first stepping stone to enabling the communication channel between…

• 2 min read
Verification IP , VIP , DisplayPort , Link Training , Design IP and Verification IP

SoC and IP

ARM-Cadence IP Deal Propels Engineering Innovation Ahead: Martin Lund

On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal…

• 6 min read
IP , electronic system design , cadence , systems engineering , IP design , ip cores , interoperability , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Cognitive Layering Technique for Low-Energy, Sensor-Rich D…

In this week's Whiteboard Wednesdays video, Chris Rowen talks about techniques for…

• less than a min read
Whiteboard Wednesdays , IP , IoT , sensors , Tensilica , always-on , power

SoC and IP

Mobile World Congress: Two New Audio IP Announcements

BARCELONA, Spain—Mobile World Congress is not surprisingly focused on mobile devices…

• less than a min read
DTS , #MWC15 , cadence , audio , audio subsystems , Mobile World Congress , IP design , Tensilica , HiFi Audio , MaxxVoice

Whiteboard Wednesdays

Whiteboard Wednesdays—Major Enhancements of the PCIe Gen 4 Specification

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , bandwidth , PCI Express , power

Life at Cadence

A Great Place to Do Great Work: Celebrating Our First Year on the FORTUNE List of…

Innovation starts with our people. For over 25 years, Cadence has been a leader…

• 4 min read
cadence , Fortune , GPTW , Lip-Bu Tan , Fortune 100 best companies to work for , great place to work

SoC and IP

IP Requirements for Verifying CHI-Based Designs

Just as IP components offload design effort, verification IP (VIP) components offload…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Design IP and Verification IP , CHI VIP

SoC and IP

Mobile World Congress: A Decade of Change in IP Innovation

BARCELONA, Spain—In the past decade, immense change has come to mobile electronic…

• 1 min read
electronic system design , #MWC15 , cadence , Steve Roddy , Mobile World Congress , Tensilica , mobile , IC design

Analog/Custom Design

Virtuosity: 12 Things I Learned In February by Browsing Cadence Online Support

Application Notes 1. Voltus-Fi Power Analysis Support and Power Grid View Generation…

• 3 min read
AMS Designer , PSPICE , Voltus , Layout , Constraints , FinFET , VLS XL

SoC and IP

WiGig Has Arrived to Enable IoT Designs--and Cut the HDMI Cord!

What is WiGig WiGig is the name given to a high-speed multi-gigabit wireless communications…

• 3 min read
wireless , cadence , IP blocks , IP design , WiGig IP , 802.11ad , wiGig , HDMI , WiFi

Whiteboard Wednesdays

Whiteboard Wednesdays - Optimizing Power Via a Configurable Processor

In this week’s Whiteboard Wednesdays, Chris Rowen takes a look at the basic energy…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , optimize power , Tensilica , energy , configurable processor , power

Analog/Custom Design

Virtuosity: 13 Things I Learned in January 2015 by Browsing Cadence Online Suppo…

'Tis the end of an era, folks. It should not be a surprise, but IC 5.1.41 reached…

• 2 min read
EAD , ADC , PLL , ADE , Spectre , Parasitic analysis

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Find Filter Support of Hierarchical Constraint…

The 16.6 Allegro PCB Editor release ‘Find by Name’ list now supports hierarchical…

• less than a min read
Cadence Design Systems , Allegro 16.6 , PCB Editor , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

Don’t Lose Extra Simulation Cycles

After reading the rest of this blog, you might guess the truth, which is that my…

• 2 min read
Specman , e , e verification code , simulation , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Cadence VIP Ease of Use Project

In this week's Whiteboard Wednesdays video, Herbert Rivera-Sanchez discusses the…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , Ease of Use

Verification

Deque to the Rescue—Introducing the e Template Library

A customer working on a VIP component identified that the performance of one of their…

• 4 min read
e Template Library , e , FIFO , eTL , deque
CDNS - Fix Layout Hompage