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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Happy Thanksgiving. Do You Have Toenailitis?

It’s Thanksgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

• 3 min read
bayes' theorem , physicians' knowledge of statistics , statistical literacy , false positive , false negative , turkey , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: ADE Explorer Setup - Save Now and Reuse Later!

Have you ever come across a situation where you have a test setup in ADE Explorer…

• 3 min read
Explorer , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuoso Video Diary , mixed signal

System, PCB, & Package Design 

Learning Advanced Flex and Rigid-Flex Design Support in Allegro 17.2-2016

Allegro PCB Editor now offers Rigid-Flex applications where it’s common to have different…

• 2 min read
Cadence Design Systems , PCB Editor , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

Future of EDA: The Q & A

There was a recent panel discussion at Cadence on the future of EDA. The panelists…

• 4 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

Future of EDA: Industry...Well, Cadence...Weighs In

There was a recent panel discussion at Cadence on the future of EDA. If you didn…

• 3 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

The Future of EDA: The View from Academia

There was a recent panel discussion at Cadence on the future of EDA. Of course the…

• 6 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Verification

A Personal History of Functional Verification

In my most recent blog post , I summarized some of the key points from an October…

• 4 min read
ASIC , uvm , pswg , formal. Verisity , Functional Verification , System Design and Verification , OVM , System Development Suite , constrained-random , Simulation acceleration , Accellera , metric-driven verification , Virtual Platforms , Hardware/software co-verification , simulation , FPGA , System Design and Verification

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Via Structures - The Next Generation High Speed…

Via transitions are very common for signals. And in high speed frequencies, these…

• 2 min read
diff pairs , Signal Intregrity , High Speed , PCB design , differential pairs , SI analysis and modeling , Differential Pair Support , Why Move Up to 17.2

Breakfast Bytes

RISC-V 5th Workshop Preview

The 5th RISC-V workshop is coming up on November 29 and 30 on the Google Quad campus…

• 3 min read
risc-v , risc-v foundation , google , risc-v workshop , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview November 21st to 25th

https://youtu.be/dHvlzjjH9SA Monday: The Academic Panel: the Academics Go First…

• less than a min read
Alberto , thanksgiving , Cadence Academic Network , academia , Stanford , cal , industry , UC Berkeley

Breakfast Bytes

JasperGold: Thoroughbred Performance

At the largest gathering of formal verification (FV) engineers in the world, also…

• 6 min read
JUG , formal , Visualize , Jasper , jaspergold apps , JasperGold , Breakfast Bytes , verification

System, PCB, & Package Design 

Why SerDes Signaling Is Trending Towards PAM Encoded Signals

What’s the difference between NRZ, PAM-3 and PAM-4? Here are three graphs that clearly…

• 2 min read
Serial link analysis , PAM-4 , Sigrity , PAM-3

Breakfast Bytes

Jürgen Went From Mobile to Automotive—What Did He Find?

After ARM on the first day, the keynote on the second day of DVCon was by NXP. For…

• 8 min read
Automotive , NXP , DVcon , ARM , Breakfast Bytes , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - MIPI Alliance Interfaces

In this week's Whiteboard Wednesdays video, Moshik Rubin takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , MIPI , MIPI protocols , DSI , CSI2

Breakfast Bytes

What Is the ARM ARM?

The first ARM is the ARM we all know, Advanced RISC Machines (the A originally stood…

• 5 min read
Jasper User Group , JUG , Jasper , ARM , JasperGold , arm arm , Breakfast Bytes , Formal verification

Breakfast Bytes

Red Hat's Mr. ARM Talks Open Source

Jon Masters is in an odd position—he is the chief ARM architect at Red Hat. Since…

• 8 min read
open source hardware , arm servers , red hat , open source software , open source , jon masters , linux , Breakfast Bytes

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Tabbed Routing - The Next Generation High Speed…

Improve Route Channel Utilization with Tabbed Routing Tabbed routing is a new…

• 2 min read
Routing , high-speed , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

Optimizing Power with Palladium

At TSMC's OIP Ecosystem Symposium, Cadence's Frank Schirrmeister presented on Software…

• 4 min read
palladium z1 , Dynamic Power Analysis , TSMC , TSMC OIP , Incisive , power , Breakfast Bytes

Breakfast Bytes

What Is Automotive Tool Confidence Level 1?

ISO 26262 is the functional safety standard for automotive, as you probably already…

• 4 min read
tcl1 , tool confidence level , ISO 26262 , Breakfast Bytes , tcl
CDNS - Fix Layout Hompage