Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines…

• 3 min read
IEEE 1647 , SystemVerilog , Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , e , OOP , ClubT , Aspect Oriented Programming , AOP , IES-XL

Digital Design

My DATE With 3DIC Technology

This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden…

• 3 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP

Analog/Custom Design

Video Demo: Your Maiden Voyage Across OCEAN

I still remember my first encounter with OCEAN. It was 2002 and my co-worker had…

• 1 min read
OCEAN-XL , ocean , ADE , Spectre , ADE-XL , Custom IC Design , SKILL

Verification

Accessing Physical Memory and Registers in a Virtual World

When working with Virtual Platforms that are running operating systems it's sometimes…

• 3 min read
Registers , Memory , virtual platforms , Virtual , System Design and Verification

System, PCB, & Package Design 

What's Good About Taray? Quite a Bit Actually!

You've probably read about all the buzz in the EDA news this week - " Cadence acquires…

• 4 min read
FPGA System Planner , Taray , OrCAD , PCB design , FPGA , Allegro

Verification

Tweeting From a Standards Meeting: Good or Bad?

In my last blog entry , I mentioned that I was able to keep up with a lot of the…

• 2 min read
uvm , tweeting , meetings , Functional Verification , texting , Accellera , EMAIL

Verification

Free eVC Generator From CFS Vision Update

In an earlier post Team Specman had the pleasure of introducing the free, open source…

• less than a min read
Specman , Functional Verification , OVM e , e , CFS Vision , FOSS , eRM

System, PCB, & Package Design 

TeamAllegro Spices Up SNUG With Allegro PCB SI

Allegro PCB SI has supported multiple simulation engines for well over seven years…

• less than a min read
PCB SI , HSPICE , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , PCB design

Verification

Crises In The Semiconductor Industry

I am on my way to Japan and I have just finished to read an excellent book and in…

• 2 min read
System Design and Verification , SoC , Semiconductor , ESL

Analog/Custom Design

Exceed On Demand And Virtuoso IC6.1

Many of our customers use our Virtuoso software in combination with the windows…

• less than a min read
IC 6.1 , OpenText , Exceed on Demand , Virtuoso , Cusstom IC Design

System, PCB, & Package Design 

What's Good About Optical Wiring On PCBs? See How Allegro PCB Editor Makes This Happen

This week, I'm taking a brief break from the usual PCB solution/product technical…

• 2 min read
Optical Wiring , OPCB , PCB Editor , PCB design , Allegro

Verification

Built-in Message Logging – Part 2 of 2

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group…

• 3 min read
Specman , debug , Functional Verification , e , Funcional Verification , Aspect Oriented Programming , AOP

Verification

UVM = OVM 2.1: Even Better!

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face…

• 1 min read
uvm , Functional Verification , OVM , Accellera VIP TSC

Verification

Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the…

• 2 min read
Specman , Functional Verification , tech tips , e , AOP , IES-XL

System, PCB, & Package Design 

What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!

You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro…

• 1 min read
AMS , AMS simulator , SPB 16.3 , PCB design , Allegro

Digital Design

Signoff-Driven Implementation = Consistent and Convergent = Predictable and Effi…

Digital designs are reaching 10's of millions of instances, which makes efficiency…

• 2 min read
timing system , dynamic rail analysis , Static timing analysis , Early Rail Analysis , Multi-Core and Parallel rocessing , Statistical , Extraction , Signoff Analysis , timing constraints , SI analysis , noise analysis , OCV , Signal Integrity , Digital Implementation , Timing analysis , Power Analysis , signoff , timing convergence

Analog/Custom Design

Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements

I'm not going to beat around the bush here. I could tell you about all the things…

• 2 min read
Virtuoso Analog Design Environment , Virtuoso , IC 6.1.4 , Custom IC Design

Verification

VIP Portfolio Extension: New AMBA 4 Protocol Support

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing…

• 1 min read
metric driven verification (MDV) , Functional Verification , vPlan , Cadence VIP portfolio , OVM , VIP , Compliance Management System , CMS , AMBA , ARM

Verification

Have You Considered e Lately?

Richard Goering's recent interview with Mitch Weaver on the future of Specman and…

• 2 min read
SystemVerilog , Specman , Testbench simulation , e , verification
CDNS - Fix Layout Hompage