Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Cadence Exec: Why Cadence is Comitted to e/Specman

In case you or your management are wondering about Cadence's commitment to supporting…

• less than a min read
IEEE 1647 , SystemVerilog , IntelliGen , Specman , Object Oriented Programming , OVM ML , Functional Verification , OVM , OVM e , e , team specman , OOP , ClubT , Aspect Oriented Programming , SystemC , eRM , Incisive Enterprise Simulator (IES) , AOP , IES-XL , Trailblazer

Verification

OVM Community Contributions: Wildly Popular And Clearly Essential

A couple of weeks ago, before going to bed one night I checked the statistics for…

• 2 min read
uvm , Verification methodology , Functional Verification , OVM , Contributions , Accellera

Verification

DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification…

• 4 min read
SystemVerilog , Specman , TLM , Object Oriented Programming , OVM ML , Functional Verification , OVM , OVM e , Incisive , e , Mike Stellfox , DVcon , OOP , AMIQ , SystemC , MDV , eRM , AOP , IES-XL

System, PCB, & Package Design 

Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

IBIS is sometimes known as the bird of knowledge, but is also the popular standard…

• 1 min read
PCB , SigXP UI , PCB Signal and power integrity , SPB 16.3 , IBIS-AMI , SerDes , PCB design

System, PCB, & Package Design 

What's Good About ASA Schematics? Numerous Improvements in The SPB16.3 Release!

Allegro System Architect (ASA) also known as System Connectivity Manager (SCM) allows…

• 1 min read
SCM , SPB 16.3 , Allegro 16.2 , ASA , PCB design , Schematic

Verification

Beyond Coverage: Adding Arbitrary Metrics To Your Metric-Driven flow

The most common metrics used in current metric driven verification (MDV) flows are…

• 3 min read
Specman , metric driven verification (MDV) , Functional Verification , vPlan , e , Enterprise Manager , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Methodology Is Important But Language Matters - Part 2

In this blog, I would like to discuss the direction in the languages that will be…

• 4 min read
High-Level Synthesis , Verification planning and management , TLM-driven design , TLM , System Design and Verification , embedded software , virtual protoype , ESL handoff , SystemC , C-to-Silicon Compiler , TLM 2.0-driven design , verification

Verification

An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog

In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Verification

Tech Tip: Easy Way To Re-Run Using The Same Seed

[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week…

• 2 min read
Specman , Funcional Verification , IES-XL

System, PCB, & Package Design 

What's Good About DEHDL Font Support? The Secret's in The SPB16.3 Release!

Well - it's here! Native font support in Allegro Design Entry HDL (DEHDL)! This has…

• 8 min read
DEHDL , SPB 16.3 , Allegroro , PCB design , Design Entry , File Directives

SoC and IP

What’s on the Horizon for NAND and DRAM?

Young Choi , Guest Blog for Denali Software January is a time where lots of…

• 4 min read

Verification

What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology…

Cadence is in the vanguard of a movement to a higher level of productivity via the…

• 3 min read
TLM , RTL , System Design and Verification , IP re-use , Synthesis , verification

Digital Design

Three Reasons to Move to EDI System 9.1

We recently announced the 9.1 version of the Encounter Digital Implementation System…

• 1 min read
Foundation Flow Design Closure , Encounter Digital Implementation System 9.1 , Digital Implementation , EDI system Encounter Digital Implementation System

System, PCB, & Package Design 

Come See TeamAllegro at DesignCon2010

A new year means another DesignCon and 2010 is an exciting year for the PCB and IC…

• 1 min read
SiP , Signal Intregrity , Allegro 16.3 , IBIS-AMI , PCB design , Desigcon

Verification

How Big Is An int?

This week I'm taking a break from my series on Android System Verification to talk…

• 8 min read
Small Device C Compiler , wishbone , z80 , OpenCores , ISX

Verification

Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend…

• 1 min read
Functional Verification , CPF , Low-Power , UPF , SystemC , IES , ESL

Verification

A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made…

• 3 min read
SystemVerilog , metric driven verification (MDV) , Functional Verification , C , EDA , e , multi-language , coverage driven verification (CDV) , SystemC , MDV , ESL

System, PCB, & Package Design 

What's Good About SiP Layout ADRC? See For Yourself Using The SPB16.3 Release!

In the SPB16.3 release, the SiP Layout Assembly Design Rules Checker (ADRC) User…

• 16 min read
SiP , DRC , SPB 16.3 , ACSET , ADRC , PCB design

Verification

Why UVM Does Not Equal OVM Plus VMM

In the numerous tweets, blog posts, and online forum discussions on the upcoming…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM
CDNS - Fix Layout Hompage