Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

12% Is Not Enough: Women in Engineering

At CDNLive EMEA, there was a Women's track and the first presentation was by Elizabeth…

• 4 min read
women's engineering society , STEM , CDNLive , CDNLive EMEA

System, PCB, & Package Design 

BoardSurfers - Aerials and Bails: Take a Walk on the Wild Side...with Auto-Roami…

We have had this question before, so it’s a good one to remind everyone of in case…

• 2 min read
APD , PCB Editor , SiP Layout

Life at Cadence

Cadence: A Great Place to Work—Asia

For the first time ever, Great Place to Work ranked Cadence as the #15 Best Place…

• 5 min read
Community , giving back , GPTW , great place to work

Academic Network

International Symposium on Physical Design 2019

The International Symposium on Physical Design (ISPD) contest is a well-known competition…

• 4 min read
ISPD , Academic Network , Innovus , ISPD 2019 Contest

Breakfast Bytes

Intel and PSS...and Simics, a Blast from My Past

One of the newest standards in verification is PSS, the Portable Stimulus Standard…

• 4 min read
Intel , DAC , Perspec , pss , portable stimulus standard

Verification

Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1…

Figure 1: The panel and crowd Citizens—the tech world is in trouble. With the ever…

• 5 min read
security , luncheon , DAC 2019 , Panel , Accellera

Breakfast Bytes

Sunday Brunch Video for 23rd June 2019

https://youtu.be/6GUoDQkSoLY Made at Paris Air Show (camera Simon Fielding) Monday…

• less than a min read
sunday brunch

Breakfast Bytes

Why Is 5G Such a Big Deal?

Yesterday was my post What Is 5G? which is the first half of my introductory look…

• 7 min read
5G , mmwave , mobile

System, PCB, & Package Design 

IC Packagers: Constructing Components from Manufacturing Data

We’ve all been there. The only (or most accurate) data that we have for a component…

• 5 min read
IC Packaging and SiP , APD , SiP Layout

System, PCB, & Package Design 

BoardSurfers - Aerials and Bails: How to Split a Viastack

Today’s compact and powerful devices require small and high-density PCBs. Tight routing…

• 2 min read
APD , PCB Editor , SiP Layout , Allegro

Breakfast Bytes

What Is 5G?

At the DAC theater, Cadence's Ian Dennison talked about 5G Intelligent System Design…

• 7 min read
5G , mmwave , IoT , mobile

Verification

Master of ‘e’? Now You Can Prove It!

The knowledge and experience of using Specman/ e tells everyone that you have acquired…

• 1 min read
Specman , Specman/e , Specman e , badge , e , e language , specman elite

Digital Design

Exploring AI / Machine Learning Implementations with Stratus HLS

A lot of AI design is done in software and, while much of it will remain there, increasing…

• 4 min read
High-Level Synthesis , TensorFlow , machine learning , Stratus , SystemC , HLS , AI

Breakfast Bytes

Assessing Bias in Computer Vision Systems

I came across a fascinating document from Facebook on methods to assess bias in computer…

• 5 min read
imagenet , Computer Vision , Facebook , convolutional neural networks , neural networks , bias

Whiteboard Wednesdays

Whiteboard Wednesdays - Passport Partners Program Expands Customer Cloud Deployment…

In this week's Whiteboard Wednesdays video, Craig Johnson explains the purpose of…

• less than a min read
Whiteboard Wednesdays , Cloud Passport , Cloud-based Design , cadence cloud

Breakfast Bytes

DAC: The View from Wall Street

Jay Vleeschhouwer did his annual...well, he did it last year, too...View from Wall…

• 4 min read
DAC , wall street , vleeschhouweer

Analog/Custom Design

Virtuoso IC6.1.8 ISR4 and ICADVM18.1 ISR4 Now Available

The IC6.1.8 ISR4 and ICADVM18.1 ISR4 production releases are now available for download…

• 4 min read
ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , Interactive and Assisted Routing , Virtuoso RF , ADE , Virtuoso Analog Design Environment , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8

Breakfast Bytes

Designing a Wi-Fi HaLow Baseband in Less than Six Months

At CDNLive EMEA last month, Stefan Stanic of Methods2Business (M2B) presented The…

• 2 min read
CDNLive , CDNLive EMEA , Stratus , high level synthesis

System, PCB, & Package Design 

DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 1 of 2)

This is the first of a two-part blog post on managing part obsolescence using Allegro…

• 3 min read
allegro edm , Library and design data management , EDM , PCB design
CDNS - Fix Layout Hompage