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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Padstack Editor – More Than Just a New GUI…

Customer inputs are key to product improvements I can read your minds as you…

• 5 min read
backdrill , Allegro 17.2 , keepouts , masks , padstack , PCB design , Why Move Up to 17.2 , Allegro

Breakfast Bytes

Signal and Power Integrity Masterclass

At CDNLive Boston, I moderated a panel session on signal and power integrity with…

• 9 min read
DDR4 , CDNLive , dc-dc converters , IBM , Cisco , Oracle , cdnlive boston , advanced bus analysis , Qualcomm , compliance methodology

Academic Network

Cadence at the VLSI Design/CAD 2016 Symposium

Great Academic Networking in Taiwan With the support of the Cadence Academic Network…

• less than a min read
VLSI , Cadence Academic Network

Academic Network

ESSCIRC and ESSDERC in Lausanne

Since the year 2000, the European Solid-State Device Research Conference (ESSDERC…

• 2 min read
Cadence Academic Network , esscirc , essderc

Computational Fluid Dynamics

Masten Space Systems: Reuseable Space Craft Innovation With Cadence CFD Software

Until very recently, rockets that launched satellites into orbit were completely…

• 5 min read

Breakfast Bytes

Are These Codecs Any Good? Netflix Tests Them

A codec compresses data for transmission. The first codec I had any close encounter…

• 5 min read
GSM , audio codec , H.265 , codec , netflix , mobile , h.264 , video codec , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview September 19th to 23rd (video)

https://youtu.be/KKiIDaN-3CE Monday: At CDNLive Boston I moderated a panel session…

• less than a min read
cdnlive tel aviv , Paul McLellan , CDNLive , debug , mellanox , VIP , MIPI , Power Integrity , i2c , cdnlive boston , mipi devcon , Indago , Signal Integrity , cdnlive israel , I3C , what's for breakfast? , protocol verification , Breakfast Bytes , verification

Breakfast Bytes

Emulation Productivity: Beyond the Specs

At CDNLive in Boston, Andrew Ross of AMD presented a wealth of practical information…

• 5 min read
CDNLive , palladium z1 , Protium , Palladium , cdnlive boston , Emulation , FPGA prototyping , Breakfast Bytes

Academic Network

Increasing Functional Verification Coding Process Efficiency

In EDA you traditionally have to know several modelling languages for several domains…

• 3 min read
eclipse , Cadence Academic Network , Functional Verification , DVT , Coding Efficiency

Breakfast Bytes

Everything That's New About Ethernet

IEEE 802.3 is the standard number for various flavors of Ethernet. With Ethernet…

• 6 min read
Ethernet standards , Ethernet , 802.3 , IEEE , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Training Different Networks Using Hierarchical CNN

In this week's Whiteboard Wednesdays video, Michelle Mao follows up on last week…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica

Breakfast Bytes

DARPA: All Must Have Prizes

At CDNLive Boston, the invited keynote was by Dr. Bill Chappell of DARPA's Microsystems…

• 4 min read
CDNLive , cdnlive boston , robotics , autonoous vehicles , craft , microsystems technology office , darpa

Breakfast Bytes

Electronic Design Automation Handbook

Way back in 2006, Luciano Lavagno, Lou Scheffer, and Grant Martin, all then at Cadence…

• 4 min read
TCAD , Electronic Design Automation , system design , EDAC , Testing , implementation , Circuit Design , process design , Breakfast Bytes , verification , book

Breakfast Bytes

Facebook's Aquila Flies...and OpenCellular

In Barcelona in February I attended a "keynote' with Mark Zuckerberg which was actually…

• 4 min read
aquila , Facebook , opencellular , zuckerberg , internet.org

Breakfast Bytes

What’s for Breakfast? Preview September 12th to 16th (video)

https://youtu.be/eDeD0mg7D54 Monday: My review of Electronic Design Automation…

• less than a min read
CDNLive , palladium z1 , AMD , H.265 , IEEE 802.3 , cdnlive boston , Ethernet , Emulation , codec , netflix , h.264 , vp9 , video codec , darpa

Breakfast Bytes

Cadence's History with MIPI

I talked last week to Kevin Yee, Sachin Dhingra, and Moshik Rubin about the history…

• 6 min read
Automotive , MIPI , mipi devcon , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Cadence Hierarchical CNN Design

In this week's Whiteboard Wednesdays video, Michelle Mao talks about Cadence hierarchical…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica , CNN

Breakfast Bytes

SiFive: a RISC-V Fabless Semiconductor Company

A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. Jack is…

• 3 min read
risc-v , fabless , sutter hill ventures , freedom unleashed , freedom everywhere , sifive , foundry

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Concurrent Team Design Capability (Reason 2…

Use teamwork to get off the critical path! When (not if) change happens or scope…

• 3 min read
Allegro 17.2 , Symphony , Real Time Design , PCB design , Why Move Up to 17.2
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