Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

BGA Ball Map Creation

Are you responsible for the creation and management of a BGA ball map or a die bump…

• 1 min read
Co-Design , IC package design , I/O planning , BGA ball map

Verification

Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But…

• 4 min read
performance , Specman , Functional Verification , Incisive , e , e language

System, PCB, & Package Design 

Designing a Complex Leadframe Package? See How SiP Layout Tool Can Cover All the…

Leadframe package designs are here to stay, and they are getting more complex with…

• 7 min read
IC Packaging and SiP Design , Cadence Design Systems , leadframe , SiP , Digital SiP design , design variants , IC package design , package design , SiP Layout , wirebonding

Verification

The Dark Side of Constraints on 'do-not-generate' Fields

The art of expressing hardware functionality through constraint language is often…

• 7 min read
IntelliGen , Specman , Functional Verification , e language , constraint coding

Verification

Debugging Multi-Language Verification Environments

As shown in previous blog posts in the Multi-Language Verification Environment series…

• 4 min read
uvm , UVM-ML , multi-language verification , debugging

Digital Design

Five-Minute Tutorial: Innovus Placement Optimization

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now…

• less than a min read
GigaPlace , Timing Optimization , Innovus , Placement

Whiteboard Wednesdays

Whiteboard Wednesdays—What Is PCI Express Address Translation Services?

In this week's Whiteboard Wednesdays video, Gopi Krishna defines and describes how…

• less than a min read
Whiteboard Wednesdays , address translation services , PCIe , PCI Express

SoC and IP

Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth…

The PCI-SIG Developers Conference happening today and tomorrow will be yet another…

• 2 min read
PCIe Gen4 , pcie gen2 , 16nm , PCIe Gen3 , PCI-SIG

Analog/Custom Design

Things You Didn't Know About Virtuoso: Help Us to Help You

There is a team at Cadence working on developing the next generation of Cadence documentation…

• less than a min read
Virtuoso , Cadence Help , online documentation , Cadence support

System, PCB, & Package Design 

Manage All Design Variant Options for Your Package Substrate Seamlessly Using 16…

Stacked memory is becoming increasingly common in IC package substrates; with that…

• 2 min read
IC Packaging and SiP Design , stacked dies , SiP , IC Package , IC Packaging , SiP Design , design variants , package design , SiP Layout

SoC and IP

Sensor Processing, How Hard Can It Be?

When I think back back just a few years ago, there were only a handful of devices…

• 2 min read
DSP , IP , IP blocks , controller , IoT , SoC , Fusion , ip cores , Processor IP , Tensilica , semiconductor IP , Internet of Things , Design IP and Verification IP , always-on

Whiteboard Wednesdays

Benefits of Designing Your SoC with a Multi-Protocol PHY

In this week's Whiteboard Wednesday video, William Chen explains the many benefits…

• less than a min read
Whiteboard Wednesdays , IP , PHY , SoC , multi-protocol

SoC and IP

Tensilica Team Wins DAC 2015 Best Paper Award

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at…

• 1 min read
IP , Chris Rowen , ip cores , vision , imaging , image processing

Analog/Custom Design

Virtuosity: 14 Things I Learned in May 2015 by Browsing Cadence Online Support

Cadence Documentation 1. Cadence Documentation Survey Cadence is committed…

• 4 min read
ADE XL , Virtuoso , Spectre

Verification

Designing a Google Ara Module and Worrying About MIPI UniPro?

So you've looked at Google project ARA and you have the most brilliant idea for a…

• 1 min read
Verification IP , UniPro , Ara , VIP , MIPI , google , TripleCheck

Verification

Aargh!!! How Can I Read Arguments from the Command Line Without argv?

Many times a user would like to be able to modify the behavior of a program based…

• 3 min read
Specman , Functional Verification , e language , simulation

Verification

Multi-Language Verification Environment (#4)—Multi-Language Hierarchy

In the previous posts in this series on Multi-Language Verification Environment,…

• 2 min read
uvm , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Digital Design

Five-Minute Tutorial: The Innovus Standard Flow

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface…

• less than a min read
design flow , Digital Implementation , Innovus , five minute tutorial

Verification

Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi…

In the previous blog post , we demonstrated connecting a checker implemented in SystemVerilog…

• 3 min read
SystemVerilog , uvm , multi-language verification , UVM Scoreboard , verification
CDNS - Fix Layout Hompage