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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL--Take This Job and...Run It!

Sometimes these articles just write themselves... Last week, 3 different people asked…

• 3 min read
Analog Simulation , analog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About AMS Simulator Fonts, Models, and More? It's in SPB16.3!

The SPB16.3 release of the Allegro AMS Simulator environment contains a few additional…

• 2 min read
SPB16.3 , AMS , AMS simulator , SPB 16.3 , PSPICE , SPB , AMS simulation , Design Entry , library

RF Engineering

Measure Twice, Cut Once for Transistor ft

Recently there was an inquiry about the methodology for performing the f t (transition…

• 3 min read
RF , Ft , ADE-L , Analog Simulation , Measuring Transistor ft , transistor , Analysis , ADE , Virtuoso , parametric , sweep

Verification

Why EDA Verification is Like Pro Sports

First, I would like to introduce myself. My name is Jim Kjellsen. I've recently joined…

• 2 min read
Functional Verification , football , pro sports , sports , Kjellsen , verification

SoC and IP

Renesas introduces new 1.1Gbit low-latency DDR DRAM (LLDRAM) for networking apps

Renesas has introduced a new 1.1Gbit, low-latency DDR DRAM (LLDRAM) primarily for…

• 1 min read

Verification

Tech Tip: Distributing Incisive Enterprise Verifier (IEV) Engines and Assertions…

A common problem when distributing engines and assertions in Incisive Enterprise…

• 1 min read
ABV , Functional Verification , Formal Analysis , formal , LSF , Enterprise Manager , IEV

SoC and IP

OCZ invents proprietary 20Gbps link for SSDs, snubbing SAS, SATA, and PCIe

Yesterday, OCZ released a curious statement saying that it was unveiling a proprietary…

• less than a min read

SoC and IP

Elpida announces 30nm, low-voltage, low-power, 2Gbit DDR3 SDRAM with TSV (through…

The headline pretty much says it all. Memory vendor Elpida hit all the DRAM high…

• 1 min read

Verification

A Quick Check on the Status of UVM 1.0

Regular readers know that I've blogged a lot about the Open Verification Methodology…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

SoC and IP

LSI Corp to host IC innovation conference and technology showcase in Milpitas next…

On October 5 through 7, LSI Corp will be hosting a conference and technology showcase…

• 1 min read

Verification

Will Your Next System Project Succeed?

Will you have the System Realization tools you need? Will you know how to apply them…

• 3 min read
TLM , webinars , system realization , TSMC , services , ARM , ESL , System Design and Verification

System, PCB, & Package Design 

What's Good About PCB SI DML Path Setting? See For Yourself in the SPB16.3 Release

With the SPB16.3 release of Allegro PCB SI , there’s a new methodology for Device…

• 4 min read
PCB SI , PCB , SI , SPB16.3 , SiP , Signal Intregrity , Digital SiP design , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , IBIS-AMI , SigWave , PCB Editor , design , PCB design , SI analysis and modeling , dml

Digital Design

Guest Blog: Using dbTransform to Translate Geometric Coordinates in Encounter

This is a guest post from JasonG at Avago. I hope you enjoy this useful piece he…

• 4 min read
Avago , dbTransform , encounter , db access , Digital Implementation , tcl

SoC and IP

New Blog: EDA360 Insider, for anyone involved with any aspect of system design

I’ve just started a new blog called the EDA360 Insider ( http://eda360insider.wordpress…

• less than a min read

SoC and IP

Samsung rolls 8Gbyte DDR3 SODIMM, Dell picks it up immediately, stuffs four into…

Samsung has announced that it is now shipping 8Gbyte DDR3 SODIMM SDRAM modules for…

• less than a min read

Verification

Video: Report From The Front Lines Of The Silicon Valley Electronics Industry With…

Lately the tone of the trade press and blogs about the Silicon Valley electronics…

• less than a min read
uvm , Functional Verification , Formal Analysis , formal , OVM , EDA360 , Chu , verification

Analog/Custom Design

Now Playing: Custom IC Videos-to-Go

I wanted to take a brief detour from my usual postings to point out a couple of new…

• 3 min read
IC 6.1 , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

DRAMeXchange ranks NAND Flash vendors for Q210. Samsung wins, again.

Last month, DRAMeXchange published rankings for the top “branded” NAND Flash vendors…

• 1 min read

Digital Design

Encounter Puzzler #2 Solution: Finding Registers Beneath a Hierarchy

Thanks to everyone who participated in this week's Encounter Puzzer . If you didn…

• 6 min read
dbGet , encounter , Digital Implementation , puzzler , tcl
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