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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Andy Walls of IBM talks about NAND Flash for Enterprise Applications

Just got back from a morning spent at the Flash Memory Summit. The last talk I listened…

• 2 min read

SoC and IP

Intel’s SSD roadmap starts appearing on the Web

Any company in the SSD business knows it must face Intel, so there’s always wide…

• less than a min read

SoC and IP

AgigA Tech DDR3 memory module combines SDRAM and NAND Flash for data backup on one…

AgigA Tech, a memory-module vendor and a subsidiary of Cypress Semiconductor, has…

• 1 min read

Verification

I Think, Therefore I Blog (Cogito Ergo In Araneam Scribo)

I realized that I have just passed the second anniversary of my first blog post…

• 2 min read
uvm , CDNLive , blog

Verification

Ericsson Selects Specman Constrained-Random Verification To Improve Efficiency And…

Sarmad Dahir of Ericsson switched from directed testing to constrained-random test…

• less than a min read
Specman , VIP , Coverage-Driven Verification , EDA , Aspect Oriented Programming , MDV , AOP , IES-XL

System, PCB, & Package Design 

What's Good About DEHDL Anchor Point Wire Stretch? It's In SPB16.3!

Just a very quick post this week on a simple, but elegant new SPB16.3 feature for…

• 1 min read
PCB , SPB16.3 , Allegro Design Entry , DEHDL , Allegro 16.3 , SPB 16.3 , Design Entry HDL , Front-end PCB design , PCB design , Design Entry , ConceptHDL

SoC and IP

The differential cost between SSDs and HDDs continue in today’s Fry’s ad. Giant flashing…

Today’s Fry’s Electronics ad on the back page of the first section of the San Jose…

• 3 min read

SoC and IP

Just what does “XXnm-class” mean for NAND Flash devices? Why the smoke? Why the mirrors…

Two days ago, I posted a short blog entry on Hynix’s new “20nm-class” 64Gbit NAND…

• 2 min read

Verification

e Templates: A Nifty Way To Create Reusable Code

Hi All, An e template (known as a parameterized type in other programming languages…

• 1 min read
IEEE 1647 , funtional verification , when sub-typing , TLM , Verification methodology , Object Oriented Programming , innovation , Functional Verification , Open Verification Methodology , when inheritance , Testbench simulation , OVM e , Coverage-Driven Verification , e , OVM-e , team specman , specman elite , OOP , coverage driven verification (CDV) , ClubT , Aspect Oriented Programming , esl tlm synthesis rtl dac estimation planning , macros , eRM , System Verification , Incisive Enterprise Simulator (IES) , hvl , IES , Coverage Driven Verification , Functional Verificatioa , OVMWorld , verification , IES-XL , Trailblazer

Digital Design

Abstracts For CDNLive! Silicon Valley 2010 Due August 22

Don't let the name CDNLive! confuse you. It's the Cadence user's group conference…

• 2 min read
Floorplanning , hierarchical design , Digital Implementation , CDNLive! , tcl

SoC and IP

Hynix initiates “20nm-class” NAND Flash production with 64Gbit devices

Hynix announced yesterday that it has begun mass production of 64Gbit NAND Flash…

• 1 min read

Digital Design

EDA Follow-The-Leader ... Signoff In The Design Flow

As a member of the EDA community, I find it interesting and somewhat frustrating…

• 1 min read

Verification

e Verification Job Postings We’ve Seen

Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification…

• 2 min read
IEEE 1647 , funtional verification , IntelliGen , Specman , methodology , Object Oriented Programming , Functional Verification , Open Verification Methodology , specman job postings , OVM e , Incisive , jobs , e , OVM-e , team specman , specman elite , OOP , job postings , Aspect Oriented Programming , eRM , IEV , System Verification , Incisive Enterprise Simulator (IES) , hvl , AOP , IES-XL , Trailblazer

Verification

TLM-driven Design And Verification Methodology Book Author Interviews

The recently published TLM-driven Design and Verification Methodology book has been…

• less than a min read
TLM , methodology , Stellfox , Balarin , Mosenson , Bailey , Watanabe , McNamara , ESL , book

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL Test Setup

In my last post , I left you in suspense, with your mouse hovering over the words…

• 4 min read
IC 6.1 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

Memcon 2010 proceedings now online

Last week’s MemCon 2010 was a blowout event, focusing on the past, present, and future…

• less than a min read

SoC and IP

The Woz Is Coming...The Woz Is Coming...The Woz Is Coming...and keynoting at the…

Just announced, Steve Wozniak will be speaking at the Flash Memory Summit this month…

• less than a min read

System, PCB, & Package Design 

What's Good About The PCB SI Model Editor? See For Yourself In The SPB16.3 Release

With the SPB16.3 release of PCB SI , the Model Editor has been added to allow you…

• 5 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , HSPICE , Signal Intregrity , Digital SiP design , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , IBIS-AMI , SigWave , PCB design , SI analysis and modeling , model editor , power

SoC and IP

Real comments on SSDs from the industry at large over at LinkedIn

It’s easy for pundits to flap their lips when speaking about SSDs. What’s harder…

• 4 min read
CDNS - Fix Layout Hompage