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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

SoC and IP

I’ve been waiting for this: water-cooled DDR3 SDRAM from Kingston

Long, long ago in a galaxy far, far away--PC motherboards carried an array of chips…

• 2 min read

SoC and IP

Motley Fool investment site discovers SSDs, gets it wrong

The Motley Fool, a famous investment book turned Web site ( www.fool.com ) just posted…

• 2 min read

SoC and IP

DRAMeXchange says DRAM market topped $10 billion in Q2

The worldwide market for DRAMs exceeded $10 billion in Q2 according to David Manners…

• 1 min read

Verification

Silicon Hive CTO: How Transaction-Based Acceleration Speeds IP Verification And Prevents…

Jeroen Leijten is Chief Technology Officer for Silicon Hive , a Dutch company that…

• 7 min read
IP , Leitjen , Acceleration , Silicon Hive , video , Palladium , SoC , Emulation , transaction-based , TBA , graphics , verification

Verification

Do Hardcopy Books Still Have Value?

As my colleagues Adam Sherer and Joe Hupcey reported last week, Cadence has just…

• 2 min read
uvm , Verification methodology , Functional Verification , OVM , VIP , Accellera , VMM

Verification

Tech Tip: Dramatically Improve Throughput With “Assertion Distributor”

There are several ways that Incisive Formal Verifier (IFV) can be set to evaluate…

• 4 min read
ABV , Functional Verification , vPlan , Fornal , Desktop Manager , IEV , IFV

System, PCB, & Package Design 

Favorite Features Of An IC Package Designer: Assembly Rule Checks

This is the third in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , package , SiP , Analog and RF SiP design , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , IC Packaging & SiP design , SPB , wirebond profile library , IC Package Physical layout and co-design , Kulicke & Soffa

System, PCB, & Package Design 

What's Good About Allegro GRE Bundle Editing? SPB16.3 Has Many New Enhancements!

The Allegro Global Route Environment (GRE) has expanded its capabilities in the area…

• 4 min read
PCB , PCB Layout and routing , SPB16.3 , global route , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , PCB design , Allegro PCB Editor , GRE , Allegro

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL

I know, it's been a long time since my last post. You see, we've finally arrived…

• 5 min read
IC 6.1 , ADE , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

Pasadena SSD Maker Foremay crams 2Tbytes into 3.5-inch SSD, 1Tbyte into 2.5-inch…

Foremay’s EC188 M-series Model-V SSDs is now available in a 2-Tbyte version for 3…

• less than a min read

Digital Design

Programmatically Capturing Cell Delay In The Encounter Digital Implementation Sy…

A while back we were talking about how to programatically troubleshoot timing violations…

• 5 min read
Static timing analysis , CTE-TCL , Digital Implementation , scripting , tcl

SoC and IP

Micron provides detailed synopses of its NAND Flash and PCM presentations at Flash…

Micron has done a very smart thing (note to marketers: take matters into your own…

• 5 min read

SoC and IP

MemCon 2010: DDR3 1GHz and Beyond--Preregistered attendance now approaching 800.…

Yesterday, preregistration attendance for MemCon 2010 jumped the 600 threshold. Today…

• less than a min read

SoC and IP

Add PNY to the growing list of memory module vendors entering the SSD fray

Memory-module vendor PNY has just announced its Optima line of 2.5-inch SSDs with…

• less than a min read

Verification

Video Interview: UVM Book Authors Sharon Rosenberg And Kathleen Meade

Earlier today a new book called "A Practical Guide to Adopting the Universal Verification…

• 1 min read
DAC , uvm , Functional Verification , OVM , DVcon , eRM , Accellera VIP TSC , VMM

SoC and IP

One Week Left: MemCon registration zooms past 600 attendees. Theme: DDR3 - 1 GHz…

You have only one more week to sign up for MemCon 2010! It’s the one day this year…

• 1 min read

Verification

System Realization Alliance -- An Industry Collaboration

System Realization is a very broad topic. It encompasses all aspects of system design…

• 1 min read
TLM , system realization , EDA360 , HLS , ESL , verification

Verification

New UVM Book Is For You And U But Not Ewe

A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the…

• 2 min read
SystemVerilog , uvm , TLM , Functional Verification , Testbench simulation , OVM , EDA360 , Register Package , OOP , Accellera , eRM , Accellera VIP TSC , IES-XL

SoC and IP

Wondering about mobile and consumer design and SPMT memory? Here’s your chance to…

This blog has discussed an up-and-coming serial memory-interface technology called…

• less than a min read
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