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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

Backchannel Training Another capability related to equalization adaptation is backchannel…

• 2 min read
Serial link analysis , IBIS-AMI , PCIe , Signal Integrity , Backchannel , Sigrity

Breakfast Bytes

Paul Kocher: Differential Power Analysis and Spectre

Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar…

• 11 min read
security , risc-v , Spectre , Paul Kocher , sifive

Digital Design

Wind of Change in Hardware Design

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I…

• 2 min read
High-Level Synthesis , deep learning , machine learning , Stratus , HLS

Breakfast Bytes

Is Big Brother Watching You?

I recently came across a fascinating piece by Paramal Satyal . He is Nepalese although…

• 6 min read
security , cookie , webbkoll , advertising

Verification

Coming to DVCon? It's Not Too Late to Sign Up!

Are you coming to DVCon this year? It’s right around the corner, but it’s not too…

• 1 min read
Functional Verification , DVcon 2018 , tutorials , event

Whiteboard Wednesdays

Whiteboard Wednesdays - Using DDR PHY Power Features to Reduce Power Dissipation

In this week's Whiteboard Wednesday video, Marc Greenberg explains the ways to optimize…

• less than a min read
Whiteboard Wednesdays , DDR PHY , Low Power DDR

Breakfast Bytes

embedded world 2018 Preview

It's nearly time for embedded world 2018 (yes, it likes to be trendy and put it all…

• 5 min read
Automotive , embedded world 2018 , 22fdx , Vision DSP , Tensilica , ADAS , GlobalFoundries

Breakfast Bytes

Why 1 Is Not a Prime Number

It's Presidents' Day and Cadence is on holiday. So time for me to write about something…

• 6 min read
PI , fundamental theorem of algebra , fundamental theorem of arithmetic , tau , central dogma of biology

Breakfast Bytes

Suddenly You Are CEO. What Do You Do Next?

We've covered sales , marketing , and application engineering . Let's go up to the…

• 7 min read
board , chief executive officer , CEO

Breakfast Bytes

What's For Breakfast? Video Preview February 19th to 23rd 2018

https://youtu.be/M3p1Luf4mtk Coming from Guangzhou, China (camera Carey Guo) Monday…

• less than a min read
cookie , Spectre , Paul Kocher , CEO , Embedded World , 3rd party cookie

Breakfast Bytes

Zombies

What is a zombie? It depends on who you ask. Venture capitalists talk about zombies…

• 8 min read
android , unix , iOS , zombie , linux , venture capital

Digital Design

Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose…

• 1 min read

Analog/Custom Design

Virtuoso Video Diary: Self-Paced Learning through Training Bytes

Cadence Education Services offers several online training courses and training bytes…

• 4 min read
training bytes , Virtuoso , Virtuoso Video Diary , Virtuoso Layout

Academic Network

3rd Tensilica Day in Hanover: Extending our Senses

Two events in a row are a coincidence, three events are a series. With these words…

• 2 min read
university , Hannover University , Cadence Academic Network , academic workshop , Tensilica

Breakfast Bytes

What Happens in a Patent Lawsuit?

One of the presentations in the exhibit hall, at the Chiphead Theater, was What Happens…

• 10 min read
expert witness , DesignCon , patent , lawyer , patent lawsuit

Whiteboard Wednesdays

Whiteboard Wednesdays - Can You Really Reduce DDR Power Dissipation by Reducing the…

In this week's Whiteboard Wednesday, Marc Greenberg examines the non-linear relationship…

• less than a min read
DDR Power , Whiteboard Wednesdays , Reduced Power DDR , Low Power DDR

The India Circuit

Rural India: Technology to the Rescue?

Last week I wrote about how mobile internet is expected to bring millions of Indians…

• 3 min read
3nethra , Forus Health , SBI Youth For India Fellowship , Rural India , Microsoft Mouse Mischief

Breakfast Bytes

9½ Years to Pluto, No Go-Arounds

Here's the scene. You are Alice Bowman, who in 2018 will give a keynote at DesignCon…

• 7 min read
pluto , mu69 , DesignCon , new horizons

SoC and IP

See You in Barcelona at MWC!

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never…

• 1 min read
DSP , IP , Mobile World Congress , ip cores , Tensilica , vision , imaging
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