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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Verification

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog…

In my last post I wrote some packet generation code to validate the claim that e…

• 4 min read
IEEE 1647 , SystemVerilog , Functional Verification , OVM , OVM e , CDV , OVM SV , e , coverage driven verification (CDV) , Aspect Oriented Programming , AOP , IES-XL

Digital Design

IR Drop Analysis: It's Not Really Necessary, Is It?

I was recently asked by an engineering manager if running IR drop analysis was really…

• 2 min read
VDD , VDD I/O , Digital Implementation , IR drop , EM Failures

Analog/Custom Design

Things You Didn't Know About Virtuoso: It's Video Time!

Just a quick post to let you know that there have recently been a whole truckload…

• 1 min read
IC 6.1 , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About Support Service And Design Bureau Providers? AcAe Can Help!

I usually discuss our SPB solution technical capabilities in my weekly blogs, but…

• 2 min read
PCB , design bureau , AcAe , Layout , PCB design , Allegro

Verification

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines…

• 3 min read
IEEE 1647 , SystemVerilog , Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , e , OOP , ClubT , Aspect Oriented Programming , AOP , IES-XL

Digital Design

My DATE With 3DIC Technology

This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden…

• 3 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP

Analog/Custom Design

Video Demo: Your Maiden Voyage Across OCEAN

I still remember my first encounter with OCEAN. It was 2002 and my co-worker had…

• 1 min read
OCEAN-XL , ocean , ADE , Spectre , ADE-XL , Custom IC Design , SKILL

Verification

Accessing Physical Memory and Registers in a Virtual World

When working with Virtual Platforms that are running operating systems it's sometimes…

• 3 min read
Registers , Memory , virtual platforms , Virtual , System Design and Verification

System, PCB, & Package Design 

What's Good About Taray? Quite a Bit Actually!

You've probably read about all the buzz in the EDA news this week - " Cadence acquires…

• 4 min read
FPGA System Planner , Taray , OrCAD , PCB design , FPGA , Allegro

Verification

Tweeting From a Standards Meeting: Good or Bad?

In my last blog entry , I mentioned that I was able to keep up with a lot of the…

• 2 min read
uvm , tweeting , meetings , Functional Verification , texting , Accellera , EMAIL

Verification

Free eVC Generator From CFS Vision Update

In an earlier post Team Specman had the pleasure of introducing the free, open source…

• less than a min read
Specman , Functional Verification , OVM e , e , CFS Vision , FOSS , eRM

System, PCB, & Package Design 

TeamAllegro Spices Up SNUG With Allegro PCB SI

Allegro PCB SI has supported multiple simulation engines for well over seven years…

• less than a min read
PCB SI , HSPICE , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , PCB design

Verification

Crises In The Semiconductor Industry

I am on my way to Japan and I have just finished to read an excellent book and in…

• 2 min read
System Design and Verification , SoC , Semiconductor , ESL

Analog/Custom Design

Exceed On Demand And Virtuoso IC6.1

Many of our customers use our Virtuoso software in combination with the windows…

• less than a min read
IC 6.1 , OpenText , Exceed on Demand , Virtuoso , Cusstom IC Design

System, PCB, & Package Design 

What's Good About Optical Wiring On PCBs? See How Allegro PCB Editor Makes This Happen

This week, I'm taking a brief break from the usual PCB solution/product technical…

• 2 min read
Optical Wiring , OPCB , PCB Editor , PCB design , Allegro

Verification

Built-in Message Logging – Part 2 of 2

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group…

• 3 min read
Specman , debug , Functional Verification , e , Funcional Verification , Aspect Oriented Programming , AOP

Verification

UVM = OVM 2.1: Even Better!

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face…

• 1 min read
uvm , Functional Verification , OVM , Accellera VIP TSC

Verification

Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the…

• 2 min read
Specman , Functional Verification , tech tips , e , AOP , IES-XL

System, PCB, & Package Design 

What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!

You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro…

• 1 min read
AMS , AMS simulator , SPB 16.3 , PCB design , Allegro
CDNS - Fix Layout Hompage