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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Bluetooth 5: Making Mobile Connectivity Seamless in an IoT…

Tired of struggling with pairing your Bluetooth devices and getting them to work…

• less than a min read
Whiteboard Wednesdays , IoT , range limitations , bluetooth , Internet of Things , mobile , Bluetooth 5 , connectivity

Breakfast Bytes

Portable Stimulus Standard

There is an Accellera working group that is developing a portable stimulus standard…

• 7 min read
54dac , DVcon , Accellera , pss , Breakfast Bytes , portable stimulus standard

Breakfast Bytes

IEDM in December—7nm Announcements

Soon it is the International Electron Devices Meeting. It takes place in San Francisco…

• 4 min read
extreme ultra violet , iedm 2016 , IBM , Samsung , TSMC , GlobalFoundries , 7nm , EUV , IEDM

Breakfast Bytes

What's For Breakfast? Video Preview November 28th to December 2nd

https://youtu.be/CUGTiPJQjuI Monday: My preview of IEDM which includes 7nm…

• less than a min read
risc-v , IBM , 7 nanometer , Perspec , Protium , Samsung , TSMC , gf , risc-v workshop , iOS , FPGA prototyping , femto-satellite , GlobalFoundries , pss , internet of space , IEDM , portable stimulus standard

Breakfast Bytes

Happy Thanksgiving. Do You Have Toenailitis?

It’s Thanksgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

• 3 min read
bayes' theorem , physicians' knowledge of statistics , statistical literacy , false positive , false negative , turkey , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: ADE Explorer Setup - Save Now and Reuse Later!

Have you ever come across a situation where you have a test setup in ADE Explorer…

• 3 min read
Explorer , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuoso Video Diary , mixed signal

System, PCB, & Package Design 

Learning Advanced Flex and Rigid-Flex Design Support in Allegro 17.2-2016

Allegro PCB Editor now offers Rigid-Flex applications where it’s common to have different…

• 2 min read
Cadence Design Systems , PCB Editor , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

Future of EDA: The Q & A

There was a recent panel discussion at Cadence on the future of EDA. The panelists…

• 4 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

Future of EDA: Industry...Well, Cadence...Weighs In

There was a recent panel discussion at Cadence on the future of EDA. If you didn…

• 3 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

The Future of EDA: The View from Academia

There was a recent panel discussion at Cadence on the future of EDA. Of course the…

• 6 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Verification

A Personal History of Functional Verification

In my most recent blog post , I summarized some of the key points from an October…

• 4 min read
ASIC , uvm , pswg , formal. Verisity , Functional Verification , System Design and Verification , OVM , System Development Suite , constrained-random , Simulation acceleration , Accellera , metric-driven verification , Virtual Platforms , Hardware/software co-verification , simulation , FPGA , System Design and Verification

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Via Structures - The Next Generation High Speed…

Via transitions are very common for signals. And in high speed frequencies, these…

• 2 min read
diff pairs , Signal Intregrity , High Speed , PCB design , differential pairs , SI analysis and modeling , Differential Pair Support , Why Move Up to 17.2

Breakfast Bytes

RISC-V 5th Workshop Preview

The 5th RISC-V workshop is coming up on November 29 and 30 on the Google Quad campus…

• 3 min read
risc-v , risc-v foundation , google , risc-v workshop , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview November 21st to 25th

https://youtu.be/dHvlzjjH9SA Monday: The Academic Panel: the Academics Go First…

• less than a min read
Alberto , thanksgiving , Cadence Academic Network , academia , Stanford , cal , industry , UC Berkeley

Breakfast Bytes

JasperGold: Thoroughbred Performance

At the largest gathering of formal verification (FV) engineers in the world, also…

• 6 min read
JUG , formal , Visualize , Jasper , jaspergold apps , JasperGold , Breakfast Bytes , verification

System, PCB, & Package Design 

Why SerDes Signaling Is Trending Towards PAM Encoded Signals

What’s the difference between NRZ, PAM-3 and PAM-4? Here are three graphs that clearly…

• 2 min read
Serial link analysis , PAM-4 , Sigrity , PAM-3

Breakfast Bytes

Jürgen Went From Mobile to Automotive—What Did He Find?

After ARM on the first day, the keynote on the second day of DVCon was by NXP. For…

• 8 min read
Automotive , NXP , DVcon , ARM , Breakfast Bytes , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - MIPI Alliance Interfaces

In this week's Whiteboard Wednesdays video, Moshik Rubin takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , MIPI , MIPI protocols , DSI , CSI2

Breakfast Bytes

What Is the ARM ARM?

The first ARM is the ARM we all know, Advanced RISC Machines (the A originally stood…

• 5 min read
Jasper User Group , JUG , Jasper , ARM , JasperGold , arm arm , Breakfast Bytes , Formal verification
CDNS - Fix Layout Hompage