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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Breakfast Bytes

MemCon: Memory for the Next Five Years

This year's MemCon keynotes were given by Hugh Durdan, VP of the IP Group at Cadence…

• 5 min read
Automotive , ddr5 , Memory , DDR4 , LPDDR4 , Enterprise , cadence , LPDDR , Micron , flash , IoT , SSD , HMC , hbc , DRAM , lpddr5 , HPC , DDR , mobile , ADAS , datacenter , Breakfast Bytes , DDR3 , LPDDR3

Verification

DVCon(x2), DVClub(x2): Portable Stimulus Is Everywhere

In my most recent blog post , I talked about the industry vision for portable stimulus…

• 4 min read
horizontal reuse , DAC , uvm , prototyping , pswg , Perspec , System Development Suite , DVClub , Emulation , DVcon , Accellera , portable stimulus , simulation , System Design and Verification

Breakfast Bytes

How Virtualization Is Changing Networking

On the second day of the Linley Processor conference, the keynote was by Bruce Davie…

• 5 min read
virtualization , linley processor conference , VMware , Linley , network virtualization , Breakfast Bytes , networking

Breakfast Bytes

What’s for Breakfast? Preview October 24th to 28th (video)

https://youtu.be/PHVpQ_-tmY8 Monday: The IoT attacks, with the biggest distributed…

• less than a min read
security , OIP , vast , Automotive , virtualization , functional safety , IoT , distributed denial of service , VMware , botnet , TSMC , vm/370 , Internet of Things , DVcon , DVCon Europe , ISO 26262 , ADAS , sophia antipolis , ddos , fusa , reliability , Virtutech

Breakfast Bytes

Andrzej Strojvas, the 2016 Kaufman Award Recipient

This year's Kaufman Award recipient is Andrzej Strojvas. He is the Keithley professor…

• 5 min read
Andrzej Strojvas , Kaufman Award , cmu , pdf solutions , EDAC , carnegie meilon university , kaufman , Breakfast Bytes , esd alliance

Academic Network

Try These Innovative Online Educational Tools

Web applications for electronics design provide an environment where users can apply…

• 6 min read
EDA Playground , Cadence Academic Network , Spicy VOLTsim , Incisive simulator , ElvisLab

Whiteboard Wednesdays

Whiteboard Wednesdays - Error Injection: Predefined and Callbacks

In this week's Whiteboard Wednesdays video, James David talks about the benefits…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , SoC

SoC and IP

3 Reasons That the Semiconductor Clouds Are Gathering

With cloud technology going vertical, everything is changing. The world is connected…

• 3 min read
CDNLive , PCIe Gen4 , virtual reality , augmented reality

Breakfast Bytes

Silicon on Nothing: the Origins of FD-SOI

Yesterday, I wrote about the new 12FDX process, which is a derivative of the original…

• 5 min read
stm , 22fdx , 12fdx , ST , Samsung , gf , silicon on nothing , FinFET , GlobalFoundries , thomas skotnicki , Breakfast Bytes , FD-SOI

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? So How Does Your Design “Stack-Up”? (Reason 5 of…

We are not talking about how your design compares to the next guys’, we’re talking…

• 4 min read
Routing , Rigid-Flex , MCAD-ECAD , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

GLOBALFOUNDRIES' Dual Roadmap

The Story So Far GLOBALFOUNDRIES had a 28nm Hi-K PolySi process. I think that…

• 5 min read
glofo , 22fdx , 12fdx , 14nm , emram , GlobalFoundries , 7nm , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: Creating Net Groups and Constraining Them with Spacing Using…

In this new age of complex designs and scaling of technology nodes, there are more…

• 4 min read
Advanced Node , Virtuoso Schematic XL , Virtuoso Video Diary , Custom IC Design , VLS XL , Virtuoso Layout Suite XL

Breakfast Bytes

How to Verify MIPI Protocols

At the recent MIPI DevCon, Cadence's Ofir Michaeli gave two presentations on verification…

• 5 min read
Verification IP , layered protocol , VIP , MIPI , mipi devcon , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview October 17th to 21st (video)

https://youtu.be/P3jRt2HEe8U Monday: GLOBALFOUNDRIES announced new nodes on their…

• less than a min read
glofo , Memory , linley processor conference , MemCon , network function virtualization , Cisco , Carnegie Mellon University , Andrzej Strojvas , VMware , Kaufman Award , 12fdx , cmu , network virtualization , pdf solutions , ST Microelectronics , GlobalFoundries , thomas skotnicki , kaufman

Breakfast Bytes

MemCon 2016: Storage Class Memory

MemCon, the annual all-things-memory conference originally started by Denali and…

• 7 min read
vertical flash , SCM , Memory , MemCon , LPDDR , flash , storage class memory , IBM , ddrx , DRAM , DDR , Breakfast Bytes

System, PCB, & Package Design 

What’s Good About Allegro PCB Editor Backdrill Capability? New Capabilities in 17…

The 17.2 Allegro PCB Editor has improved backdrill capabilities. Backdrill data…

• 3 min read
PCB , PCB Layout and routing , Allegro 17.2 , Allegro GUI , layer stacks , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Why Move Up to 17.2 , Allegro

Breakfast Bytes

Cache Coherency Is the New Normal

You hear a lot about cache coherency these days. In fact, at the recent Linley processor…

• 6 min read
linley processor conference , linley group , Arteris , Linley , cache coherent , cache coherency , netspeed , cache , ARM , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Driving Forces and Design Concerns Behind PCI Express Ge…

In this week's Whiteboard Wednesdays video, the second in a two-part series, Lana…

• less than a min read
Whiteboard Wednesdays , PCIe , PCI Express Gen4 , PCI Express

System, PCB, & Package Design 

Welcome to the Signal Integrity and Power Integrity Community

This is your resource for all things regarding Signal Integrity and Power Integrity…

• less than a min read
PCB , SI , PI , IC Package , Power Integrity , Signal Integrity
CDNS - Fix Layout Hompage