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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Academic Network

Successful Speaker Event—Engaging with Professor in Shanghai

The Cadence Academic Network hosted an Academic Speaker Series event, in collaboration…

• 2 min read
university , Cadence Academic Network , academia , university program

Breakfast Bytes

What Does P≠NP Mean?

Recently I wrote about computational software and said that EDA algorithms are all…

• 6 min read
NP-complete , computational software , np-hard

Analog/Custom Design

Virtuosity: Usability Enhancements in the Property Editor

Goes without saying that the Property Editor is the most frequently used feature…

• 2 min read
ICADVM18.1 , Virtuoso Layout Suite L , Property Editor , Custom IC Design , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

Die-to-Die Interconnect: The UltraLink D2D PHY IP

One of the big trends that has been happening somewhat below the radar is the growth…

• 5 min read
system in package , SiP , chiplet , more than Moore , 3D packaging

System, PCB, & Package Design 

IC Packagers: Plan Your Escape with Modernized Structures

Many of you, our regular readers, are familiar with via structures. These reusable…

• 3 min read
17.4 , APD

Life at Cadence

Asking Our Employees: What Makes Us Great in Europe?

As the project manager of our global Great Place to Work programs, I’ve had the opportunity…

• 6 min read
Culture , Community , giving back , GPTW , great place to work

Analog/Custom Design

Virtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part III

This is the third blog in the multi-part series that aims at providing in-depth details…

• 8 min read
ICADVM18.1 , Virtuoso Layout EXL , Virtuoso RF , Layout EXL , Electromagnetic analysis , Virtuoso , Custom IC Design

System, PCB, & Package Design 

What's in a Name? From Allegro EDM to Pulse in 17.4-2019

Allegro EDM (Engineering Data Management) 17.4-2019 is out! So, what's in it for…

• 4 min read
allegro edm , what's new , 17.4-2019 , PCB design , Pulse

Breakfast Bytes

The 2019 Jasper User Group

Last week was the Jasper User Group meeting, the biggest annual gathering of formal…

• 4 min read
Jasper User Group , formal , Jasper , JasperGold , Formal verification

Academic Network

Exciting Academic News on OrCAD

There’s some exciting news about the Cadence OrCAD® Software , especially for academics…

• 2 min read
PCB , academia , Contest , OrCAD , university program

PCB、IC封装：设计与仿真分析

隐藏在PCB设计中的七个DFM问题

本文由Cadence的北美经销商EMA Design Automation撰写。 space 当我们完成设计并将其送到制造厂后，如果我们的产品存在大量可制造性设计…

• less than a min read
Chinese blog , DesignTrue DFM Technology , 可制造性设计 , PCB设计 , 中文 , DFM , Allegro

Breakfast Bytes

OpenTitan: Secure Boot with a Silicon Root of Trust

At HOTCHIPS last year, Google presented its security processor Titan. You can read…

• 3 min read
opentitan , open source hardware , google , open source

Digital Design

Library Characterization Tidbits: Reasons to Start Following This New Blog Serie…

Library Characterization Tidbits is a blog series aimed at providing insight into…

• 1 min read
Liberate AMS , videos , Liberate LV , Liberate Variety , library characterization , Application Notes , Liberate MX , training bytes , Liberate , Liberate Characterization Portfolio , RAKs

Breakfast Bytes

Computational Software

This is the third post in a series on computation in EDA and adjacent markets. The…

• 4 min read
computational software

Academic Network

ECE Master Students of Duke Kunshan University Visited Cadence Shanghai Office

The Cadence Academic Network was very excited to host students from Duke Kunshan…

• 2 min read
university , Cadence Academic Network , university program

Analog/Custom Design

Virtuoso Video Diary: Click – Take a Snapshot – Smile!

This blog talks about about the Snapshots feature introduced in ADE Verifier in IC6…

• 4 min read
verifier , Analog Design Environment , ICADVM18.1 , Functional Verification , Formalized Verification , snapshots , ADE Verifier Snapshots , ADE , Mixed-Signal , Virtuoso , cadenceblogs , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , Verifier new feature , verification

Breakfast Bytes

Tempus Power Integrity Solution

One of the challenges in leading-edge nodes today is the resistivity of the interconnect…

• 3 min read
Tempus , Voltus , signoff

Verification

Specman: Analyze Your Coverage with Python

In the former blog about Python and Specman: Specman: Python Is here! , we described…

• 8 min read
Specman , Specman coverage engine , coverage , Python , Functional Verification , Specman e , e , e language , specman elite , functional coverage

System, PCB, & Package Design 

IC Packagers: Scripting Updates in 17.4

If you joined us last week to see the visual changes to be expected when you download…

• 5 min read
APD , PCB Editor
CDNS - Fix Layout Hompage