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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

SoC and IP

SanDisk and NDS collaborate to add features and video on demand to set-top boxes…

NAND Flash vendor SanDisk and set-top box software vendor NDS Group Ltd are collaborating…

• less than a min read

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 3

This is my third and final blog entry in a series using quotes from famous Hollywood…

• 3 min read
vPlan , verification planning , metric-driven verification , Hollywood , MDV , IP modeling , verification

Digital Design

Encounter 101: Implementing ECOs with ecoDesign

When people say "ECO" in the context of back-end digital implementation tools, they…

• 2 min read
ECO , encounter , Digital Implementation , ecoDesign

SoC and IP

Late Event Notice: The Makers of the Microchip: Creating the Planar Integrated Circuit…

You still have two weeks to sign up for an extremely interesting lecture titled …

• 1 min read

SoC and IP

IEEE Spectrum article provides more insight into HP/Hynix memristor pact

Despite some obvious technical flaws (DRAM cost/bit is not 10x less than NAND Flash…

• less than a min read

Digital Design

Encounter Puzzler Solution: Where Did My Fences Go?

A couple of days ago I posted a puzzler on a scenario where fences couldn't be seen…

• 3 min read
fences , Floorplanning , encounter , Digital Implementation , puzzler

SoC and IP

Pliant trades off firmware complexity against MLC NAND Flash capacity in enterprise…

The multiplicative storage capacity of MLC (multi-level cell) NAND Flash is a siren…

• 1 min read

SoC and IP

Samsung sees continuing strong demand for NAND Flash

Yesterday, I wrote that Samsung was sending caution messages about DRAM demand based…

• less than a min read

SoC and IP

Is the latest DRAM bobsled run already coming to an end? Samsung and Hynix say “Maybe…

The semiconductor business has been cyclic ever since it came into existence half…

• 1 min read

Verification

Tech Tip: Save Steps With Automatic Witness Checks

This is just a quick reminder that the "witness_check" define command has an option…

• less than a min read
ABV , Functional Verification , Formal Analysis , formal , IEV , IFV

SoC and IP

Icy Dock internal multi-drive bay crams four 2.5-inch drives (SATA or SAS) into 5…

OK, so this blog entry isn’t about memory so much as it’s about a cool ancillary…

• 1 min read

SoC and IP

Super Talent caches Flash memory on USB 3.0 drive with 32 Mbytes of DRAM, performance…

There’s been plenty of discussion about using NAND Flash memory to cache HDDs and…

• 1 min read

Digital Design

Encounter Puzzler: Where Did My Fences Go?

A while back I visited a customer I see on a fairly regular basis. As soon as I entered…

• 1 min read
fences , Floorplanning , encounter , Digital Implementation , puzzler

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Polygon Selection? Look at SPB16.3 and See!

The Allegro PCB Editor allows selection of items by several means. In preselect mode…

• 1 min read
polygon , PCB , SPB16.3 , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , PCB design , Allegro PCB Editor , PCB Capture , Allegro

SoC and IP

SD Association adds pins to SD card format to boost transfer rates to 300 Mbytes…

Hot on the heels of the rollout of high-speed SDHC and SDXC UHS-I cards that approach…

• less than a min read

SoC and IP

Toshiba to ship 32-Gbyte SDHC UHS-I cards with 95/80-Mbytes/sec read/write speed…

If you’re a rabid fan of Canon dSLRs, you already know of the many controversial…

• 1 min read

SoC and IP

Rice U’s silicon-oxide memristor more phenomenon than device, for now

Last Friday, I wrote about a memristor development out of Jim Tour’s nano research…

• 3 min read

SoC and IP

Update on Viking’s SATADIMM SSD--no cable needed, Sandforce SSD controller

Previously, I wrote about Viking’s SATADIMM, an SSD built into a standard DDR DIMM…

• 1 min read

Verification

Users Employ Specman Constrained-Random Verification for Complex IP

Two recent customer examples have shown the effectiveness of Specman constrained…

• 1 min read
SystemVerilog , Specman , metric driven verification (MDV) , Cadence VIP portfolio , VIP , Coverage-Driven Verification , EDA , Funcional Verification , Incisive Enterprise Simulator (IES) , AOP , IES-XL
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