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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About ADW’s Flow Manager? Check Out the ADW16.3 Release and See!

The ADW16.3 Allegro Design Workbench has a desktop cockpit that allows engineers…

• 4 min read
PCB , SPB16.3 , Allegro Design Entry , part developer , DEHDL , mechanical parts , Directive Lockhing , Allegro 16.3 , SPB 16.3 , High Speed , Allegro Design Workbench , Library flow , SPB , LRM , PCB Editor , Design Entry HDL , design data management , design , Library Revision Manager , "PCB design" , PCB design , Design Entry , ADW 16.3 , Allegro PCB Editor , Librarians , ConceptHDL , library , ADW , Schematic

Verification

Video: Optimizing Area and Power Using Formal Methods

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel…

• 1 min read
Low Power , ABV , methodology , Formal Analysis , formal , Freescale , Incisive , Chris Komar , DVcon , IFV

Verification

Video: New Cadence Verification IP Catalog (With Denali Inside!)

Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news…

• less than a min read
uvm , Functional Verification , ABVIP , Cadence VIP portfolio , OVM , VIP , EDA360 , Verification IP modeling , DVcon , eRM

Verification

TLM 2.0, UVM 1.0 and Functional Verification

The DVCon 2011 conference was held this week and the Accellera Universal Verification…

• 8 min read
SystemVerilog , uvm , TLM , Functional Verification , OVM , TLM 2.0 , ports , DVcon , Accellera , SystemC , Accellera VIP TSC , VMM , verification

Verification

DVCon? Are You Sure It's Not UVMCon or MSVCon?

As I write this, I've just returned from the most important conference and tradeshow…

• 2 min read
uvm , Functional Verification , MSV , EDA360 , Mixed-Signal , random test , DVcon , Accellera , mixed signal , verification

System, PCB, & Package Design 

What's Good About Cadence Online Support Product Pages? – Check Out This List!

I wrote about the new Cadence Online Support features in one of my blog posts last…

• 2 min read
PCB SI , PCB , SCM , PCB Layout and routing , SI , SPB16.3 , Allegro Design Entry , AMS , SiP , PCB PI , IC Packaging , Design Entry CIS , social networking , Signal Intregrity , DEHDL , FPGA-PCB Co-Design , Digital SiP design , specctra , SigXP UI , FPGA System Planner , OrCAD Capture , Allegro 16.3 , Capture CIS , Capture-CIS , High Speed , APD , Support , Smoke Analysis , SigWave , SPB , webinar , SPB16.2 , PCB Editor , Constraint Manager , Design Entry HDL , ASA , Layout , design , FSP , OrCAD , PCB Signal integrity , PCB design , Design Entry , windows 7 , Allegro PCB Editor , Librarians , SI analysis and modeling , ConceptHDL , SPB16.01 , OrCAD PCB Editor , GRE , Online Support , library , ADW , PCB Capture , Schematic , FPGA , Allegro

Verification

Specman Application Note: Improving Verification Productivity With Dynamic Load and…

Are you looking for new approaches to improve your verification productivity by 40…

• 3 min read
IntelliGen , Specman , metric driven verification (MDV) , Functional Verification , vPlan , simvision , EDA , Incisive , e language , team specman , specman elite , Aspect Oriented Programming , testbench , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Digital Design

Encounter Puzzler #3: Renaming a Net Logically

The other day a designer E-mailed me: How can we rename a net in Encounter? I followed…

• 1 min read
dbGet , Encounter Digital Implementation , puzzler , tcl

Verification

Do You Have a DATE with Software? Cadence Does!

How important is the software market to Cadence and as an element of the EDA360 vision…

• 3 min read
DATE , IP , IP-XACT , debug , RTL , System Design and Verification , SoC , virtual prototype , software , Virtual Platforms

Verification

At DVCon 2011 Next Week

Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you…

• 2 min read
Industry Insights , ABV , TLM , Functional Verification , formal , OSCI , OVM , EDA360 , Coverage-Driven Verification , EDA , Mixed Signal Verification , Incisive , Mixed-Signal , DVcon , OOP , multi-language , SystemC , Formal verification , techtorial , AOP

Verification

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Don't lose touch with what's new in the world of SystemC! Cadence is a long time…

• 2 min read
virtual platforms , virtual prototypes , System Design and Verification , OSCI , DVcon , Accellera , Jim Hogan , IEEE P1666 , SystemC , NASCUG , SystemC Day

Digital Design

Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Si…

Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a…

• 2 min read
dynamic rail analysis , Static timing analysis , ets , EDI system , Signoff Analysis , DRC , design rules , LVS , SI analysis , EPS , noise analysis , EDI 10.1 , Virtuoso , Digital Implementation , In-Design Signoff , Timing analysis , Power Analysis , signoff , tapeout , IR drop , Digital end-to-end flow , EM Failures , timing convergence , DFM

Analog/Custom Design

Q&A: IBM Modeling Team Describes Advanced SOI Qualification Flow In Cadence MMSIM…

Circuits implemented using sub-micron technologies require designers to meet tighter…

• 9 min read
APS , characterization , Compact Modeling Council , model qualification , IBM , MMSIM , Monte Carlo , spectreMDL , Spectre , CMC , SOI , Custom IC Design , Spice model verification , BSIMSOI

System, PCB, & Package Design 

What's Good About PCB SI Signal Quality Screening? SPB16.3 has a Few New Enhancements

Signals are subject to degradation when they are transmitted through a channel. High…

• 3 min read
PCB SI , PCB , SI , SPB16.3 , Signal Intregrity , SigXP UI , Allegro 16.3 , SPB 16.3 , High Speed , SPB , PCB design , signal quality screening , SI analysis and modeling , Allegro

Verification

Celebrating the UVM 1.0 Release, or the Gadfly Eats a Little Crow

As I hope you have all seen by now, Accellera has announced the official production…

• 2 min read
uvm , methodology , Functional Verification , VIP , VIP-TSC , Register Package , Accellera , gadfly , verification

Verification

The Increasing Role of SystemC in System Design

Today's post is less technical and a bit more theoretical, but I promise that my…

• 4 min read
debug , C , system design , SystemC , Virtual Platforms , Synthesis , Modeling , C++ , debugging , simulation , System Design and Verification

Verification

Formal Driven MDV – A New Tool for your Toolbox

Have you considered adding formal to your metric driven verification flow? Maybe…

• 2 min read
metric-driven , coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , MDV , simulation , Formal verification

Verification

Being a Part of Something Truly Remarkable - UVM

For just over two years I have had the honor of playing a role in a dramatic example…

• 2 min read
uvm , Functional Verification , EDA360 , Incisive , Accellera VIP TSC , synopsys , IES , Mentor

Verification

The Tale of the Silicon Re-Spin and the Bug That Got Away

I'd like to continue my blog series discussing corner-case conditions of various…

• 4 min read
conformal , corner cases , clock domain crossings , CDC , bug , FIFO
CDNS - Fix Layout Hompage