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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Can You Really Reduce DDR Power Dissipation by Reducing the…

In this week's Whiteboard Wednesday, Marc Greenberg examines the non-linear relationship…

• less than a min read
DDR Power , Whiteboard Wednesdays , Reduced Power DDR , Low Power DDR

The India Circuit

Rural India: Technology to the Rescue?

Last week I wrote about how mobile internet is expected to bring millions of Indians…

• 3 min read
3nethra , Forus Health , SBI Youth For India Fellowship , Rural India , Microsoft Mouse Mischief

Breakfast Bytes

9½ Years to Pluto, No Go-Arounds

Here's the scene. You are Alice Bowman, who in 2018 will give a keynote at DesignCon…

• 7 min read
pluto , mu69 , DesignCon , new horizons

SoC and IP

See You in Barcelona at MWC!

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never…

• 1 min read
DSP , IP , Mobile World Congress , ip cores , Tensilica , vision , imaging

Breakfast Bytes

Advanced Packaging Needs Advanced Tools

At the recent DesignCon, Cadence's John Park presented Advanced Packaging Trends…

• 5 min read
vsdp , virtuoso system design platform , Virtuoso , OrbitIO , more than Moore , 3D packaging

SoC and IP

What I Learned About System Design Enablement at DesignCon

While attending the recent DesignCon show for the first time, I was struck by the…

• 2 min read
IP , IP integration , SDE , Sigrity , system design enablement

SoC and IP

A Walk Through DesignCon Turns Into a Long Journey

Have you ever attended the DesignCon show? I attended the recent event for the first…

• 2 min read
IP , IP integration , SDE , noise , Sigrity

Breakfast Bytes

Application Engineers Are Like Gold

I wrote recently about my experiences Running a Salesforce , and one of the key aspects…

• 4 min read
application engineers

Analog/Custom Design

Virtuoso Video Diary: Stranded Wire – A New Sapling in Interactive Routing

In order to drive high current and to minimize routing resistivity, it is desirable…

• 3 min read
interactive coloring , stranded wire , Virtuoso Space-based Router , weStrandedColorMode , leHiCreateStrandedWire , blockage avoidance , weStrandedAlignCollinearMode , Virtuoso , Stranded Wire Context-sensitive Menu , Virtuoso Video Diary , tieout , weStrandSpacing , tapering in stranded wire , Custom IC Design , WSP support in Stranded Wire , space based router , Custom IC , weStrandedLadderAtTurn , weStrandNum

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (6 of 8)

Simulating with IBIS-AMI Models By this point in the process, the SerDes component…

• 3 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

Warsaw to Canary Islands to Madrid to Staten Island to California: Michal's Jour…

Some people grow up in the US, go to high school, get into a good engineering or…

• 8 min read
logical equivalence checking , LEC , Stanford , verplex , Berkeley , Poland , Formal verification

Breakfast Bytes

What's For Breakfast? Video Preview February 12th to 16th 2018

https://youtu.be/wwioFa3JGuc Coming from the Cadence basketball court (camera…

• less than a min read
PCB , pluto , packaging , patent , more than Moore , PCB design , zombie , CEO

Breakfast Bytes

Oz and Ziyad Look to the Future of JasperGold

At last year's Jasper User Group, the two-day event was opened by Oz Levia, VP of…

• 4 min read
Jasper User Group , JUG , formal , JasperGold , Formal verification , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Dual Channel DIMMs for Server Applications

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty, discusses how future…

• less than a min read
Whiteboard Wednesdays , Dual Channel DIMM , DIMM

Analog/Custom Design

Integrating AMS IP in SoC Verification Just Got Easier

Typically, analog designers verify their AMS IP in schematic driven, interactive…

• 1 min read
AMS , mixed signal solution , Mixed-Signal , analog/mixed-signal , Virtuoso , mixed signal , Virtuoso environment , mixed-signal verification

Breakfast Bytes

Fooling Neural Networks

I wrote recently about various aspects of modeling , not just transistor models,…

• 4 min read
security , neural networks , CNN

Breakfast Bytes

The Old Order Changeth: Samsung Takes the Crown

The most famous line of Tennyson's poem Morte D'Arthur is "The old order passeth…

• 6 min read
Intel , Memory , flash , Samsung , mobile

Analog/Custom Design

Virtuosity: Sharing Custom SKILL Calculator Functions

Have you ever written a fantastic piece of SKILL to carry out a calculation and wanted…

• 3 min read
Analog Design Environment , ADE Explorer , Virtuoso , ViVA , Custom IC Design , SKILL , ADE Assembler

Breakfast Bytes

DesignCon: PCB and Packaging Take Center Stage

You wouldn't really know it from the name, but DesignCon is all about the design…

• 8 min read
si/pi , EMI , DesignCon , deep learning , Power Integrity , machine learning , Signal Integrity , dnn , CNN , neural network
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