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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

IC Packagers: Guiding Your Team with Workflows

The flow for efficiently and correctly designing a package substrate layout is a…

• 5 min read
APD

Breakfast Bytes

Sunday Brunch Video for 22nd December 2019

https://youtu.be/iEuzyt_6O_A Made in my living room (camera Carey Guo) Monday: The…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

如何利用Allegro SiP Layout工具5步实现复杂引线框架封装的完整设计？

文章翻译自Cadence博客“ Designing a Complex Leadframe Package? See How SiP Layout Tool Can…

• less than a min read
Chinese blog , SiP , SiP设计 , 引线框架 , 中文 , 封装设计 , IC封装 , SiP Layout

Academic Network

Cadence Co-organized the First EDA Competition to Help China Train More EDA Tale…

The first “China IC and EDA Design Elite Competition” started in June 2019 and received…

• 2 min read
university , Cadence Academic Network , academia , EDA

Breakfast Bytes

Off-Topic: 2019 TV Anniversaries

It's the day before a holiday. Or in this case, ten days when Cadence will be shut…

• 6 min read
off-topic

Digital Design

Library Characterization Tidbits: A Matrix for Your Reference

When working on multiple tools of the Cadence Liberate Characterization Portfolio…

• 2 min read
parameter , Liberate AMS , Matrix , liberate blog , Liberate LV , Commands , Liberate Variety , Liberate MX , Liberate , Liberate Characterization Portfolio

Breakfast Bytes

IEDM 2019: An Overview...Plus the Future of EUV

IEDM, the International Electron Devices Meeting, took place last week. It was also…

• 6 min read
EUV , IEDM

Analog/Custom Design

Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization…

2019 was quite an eventful year for Virtuoso  ADE Product Suite and Virtuoso  Visualization…

• 4 min read
ADE waveform window , Cadence blogs , ICADVM18.1 , ADE Explorer , virtuoso visualization and analysis , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler

Digital Design

2019 Annual HLS Survey Results

Each year, we survey the industry to get an idea of the industry’s experiences and…

• 2 min read

Breakfast Bytes

System in Package? How to Plan and Build It

This is a follow on to my previous two pieces about system-in-package (SiP) designs…

• 3 min read
system in package , chiplet , 3DIC , OrbitIO

System, PCB, & Package Design 

BoardSurfers: Four Reasons to Use Allegro ECAD-MCAD Library Creator

The Cadence  Allegro  ECAD-MCAD Library Creator helps you easily synchronize ECAD…

• 3 min read
Library Creator , 17.4-2019 , ECAD-MCAD Library Creator , PCB design

System, PCB, & Package Design 

IC Packagers: An Introduction to Allegro Package Designer Plus in 17.4

Some of you are APD users, building single-chip or non-stacked multi-chip packages…

• 5 min read
17.4 , APD , SiP Layout

Breakfast Bytes

What's Happening in RISC-V Land?

Last week was IEDM, the International Electronic Devices Meeting. I will write about…

• 5 min read
Western Digital , risc-v , NVIDIA , risc-v summit , Samsung , Qualcomm

System, PCB, & Package Design 

DATA Pulse: Speed up ECAD Part Search in Allegro System Capture

Do you often search for parts when creating Allegro System Capture projects? Yes…

• 2 min read
Cadence Design Systems , Library and design data management , PCB design , Allegro System Capture , Part Search

Breakfast Bytes

The Most Important Operating System Ever

I wrote recently about Brian Kernighan's memoir and history in Brian Kernighan's…

• 7 min read
android , unix , iOS , MacOS , linux

Academic Network

2019 Workshop on Electronic Design Automation in Hsinchu Taiwan

The Cadence Academic Network has been supporting the Workshop on Electronic Design…

• 1 min read
university , Taiwan , Cadence Academic Network , academic workshop , academia , university program

PCB、IC封装：设计与仿真分析

图文详解：如何在PowerSI中为封装体上添加假性球体和参考层？

本文由Cadence经销商之一的北京耀华创芯电子科技有限公司整理撰写。耀创科技专注于电子设计自动化（EDA）服务，在引进国外先进EDA工具的同时，针对中国市场特殊性…

• less than a min read
SI , Chinese blog , 中文 , Sigrity , IC封装 , S参数 , PowerSI

Breakfast Bytes

Known Good Die

Do you know what known good die are? Do you know what wafer sort is? Final test?…

• 6 min read
system-in-package , kgd , 3DIC , known good die

Breakfast Bytes

Brian Kernighan's Memoirs

If you have ever worked on placement or floorplanning, and probably some other areas…

• 7 min read
CDNS - Fix Layout Hompage