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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

RF Engineering

Measurement of Phase Noise in Oscillators

The other day, I happened to sneak out some time for myself after having sent the…

• 1 min read
HBnoise , HB , Spectre RF , pnoise , phase noise , harmonic balance , pss , Oscillator

Analog/Custom Design

Virtuoso: The Next Overture – Introducing Design Planner

Watch out for our new layout design capability that allows you to plan more efficiently…

• 2 min read
Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , New in EDA , Custom IC Design , Design Planner , Custom IC , Layout Editing

Breakfast Bytes

PCAST: The President's Council of Advisors on Science and Technology

In January 2017, a report Ensuring Long-Term U.S.Leadership in Semiconductors was…

• 6 min read
electronics resurgence initiative , Hennessy , magestic , pcast , eri , darpa

Breakfast Bytes

What's For Breakfast? Video Preview September 10th to 14th 2018

https://youtu.be/iv9wdAVB6vg Coming from CDNLive India (camera Seena Shankar) Monday…

• less than a min read
meltdown , CDNLive India , CDNLive , Spectre , hot chips

Breakfast Bytes

Numbers Everyone Should Know

At the recent HOT CHIPS, Paul Turner of Google Project Zero talked about numbers…

• 5 min read
cpu speed , cache , networking

Breakfast Bytes

GLOBALFOUNDRIES Drops 7nm to Focus on Other Geometries

GF put out a press release last week with the title GF Reshapes Technology Portfolio…

• 4 min read
Intel , AMD , Samsung , TSMC , 5nm , GlobalFoundries , 7nm , EUV

Academic Network

APAC IC Design Contests

China Graduate IC Design Contest Contest Duration: April – August 2018 This is Cadence…

• 1 min read
apac , Cadence Academic Network

Whiteboard Wednesdays

Whiteboard Wednesdays - What You need to Know About ISO26262-2018 2nd Edition

In this week's Whiteboard Wednesdays video, the first in a multi-part series, Scott…

• less than a min read
Whiteboard Wednesdays , ISO 26262

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之2：新的实时并行团队设计功能

利用团队设计实现快速设计 无论如何，PCB团队设计总是实现快速设计的最佳捷径。您可以使用Allegro 17.2 2016版本中新的实时并行团队设计功能，通过动态分配资源来应对设计周期不断缩短的挑战…

• less than a min read
PCB , Chinese blog , Allegro 17.2 , Symphony , PCB设计 , 中文 , 实时设计 , Allegro升级17.2

Breakfast Bytes

Ambit Design Systems

Twenty years ago today, Cadence announced it was acquiring Ambit Design Systems.…

• 5 min read
ambit , Synthesis , buildgates

Breakfast Bytes

Labor Day Off-Topic: Almost Everyone Has More Than the Average Number of Legs

It's Labor Day. Cadence is closed in the US. Unfortunately, I'm in India and it's…

• 5 min read
math , off-topic , mathematics

Analog/Custom Design

Virtuosity: Opening Old ADE States and Views with ADE Explorer and ADE Assembler

Have you found it a pain that when opening a Virtuoso ADE L state or a Virtuoso ADE…

• 2 min read
Explorer , ADE Migration , ADE , Virtuoso Analog Design Environment , Analog Design Environment , Virtuosity , IC6.1.7 , Custom IC Design , Assembler

Analog/Custom Design

Virtuoso IC6.1.7 ISR22 and ICADV12.3 ISR22 Now Available

The IC6.1.7 ISR22 and ICADV12.3 ISR22 production releases are now available for download…

• 2 min read
Analog Design Environment , ICADV12.3 , ADE Explorer , ADE , Layout , Virtuoso , IC6.1.7 , Custom IC Design , Custom IC

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之1：先进的柔性和刚柔结合板设计支持

为何要刚柔结合？ 对几乎所有应用，客户一直希望能有更小、更轻、性价比更高的产品。竞争压力也促使设计工程师们以不断增长的速度将这些新产品带到市场。设计工程师们可使用柔性PCB材料…

• less than a min read
PCB , Chinese blog , Allegro 17.2 , PCB设计 , 中文 , MCAD-ECAD , IPC-2581 , Allegro PCB编辑器 , 刚柔结合设计 , Allegro升级17.2 , 刚柔结合

Breakfast Bytes

HOT CHIPS Tutorial: On-Device Inference

The Sunday of the annual HOT CHIPS (the 30th!) conference is tutorial day. In the…

• 5 min read
deep learning , inference , Tensilica , hot chips , inferene , neural networks

Breakfast Bytes

Breakfast Buffet for August

https://youtu.be/elQgyXvkcjU The three highlighted posts for August were: Two…

• less than a min read
shockley , jobs , eri , darpa

定制IC芯片设计

Virtuoso: 新序曲—设计意图工具（Design Intent）工具简介

简化设计目标， 并且给版图设计师们提供更多自由来实现他们的设计目标。

• less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso Design Intent , Virtuoso Schematic XL , Layout design , Constraints , Custom IC Design , Custom IC , Schematic , Virtuoso Layout Suite XL

Verification

Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So Much…

One animation video - Patch Like The Wind - is worth a thousand words :) If you…

• 2 min read
Specman , Specman/e , Functional Verification , Specman e , tech tips , e language , team specman , save and restart

Breakfast Bytes

Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter

At the recent HOT CHIPS conference, Scott Johnson of Google talked about some challenges…

• 6 min read
security , titan , google , supply chain , secure boot
CDNS - Fix Layout Hompage