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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

Dark Silicon: Not a Character from Star Wars

Dark Silicon may sound like a character from the latest Star Wars movie, but it actually…

• 6 min read
Dennard scaling , Dark Silicon , moore's law , dennard , multicore

Breakfast Bytes

EDAC Becomes...You Have to Be There to Be the First to Know

When Bob Smith took over as the Executive Director of EDAC, I called him up and one…

• 2 min read
bob smith , EDA Consortium , EDAC , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Implementation of Higher Speed PCIe Gen4 IP

In this week's Whiteboard Wednesday's video, Gopi Krishnamurthy highlights how Cadence…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , PHY IP , PCIe , PCI Express

Breakfast Bytes

The Economist on the End of Moore's Law

"The number of people predicting the end of Moore's Law doubles every two years.…

• 3 min read
Intel , The Economist , moore's law , FinFET

Breakfast Bytes

A Brief History of Cadence: The Solomon-Costello Era

Cadence has grown from a small startup to a $1.7B corporation. Its history includes…

• 3 min read
Jim Solomon , ECAD , Joe Costello , SDA

System, PCB, & Package Design 

Designing a New Component from Scratch Inside Your Layout Environment

Have you ever needed to build a component with a custom, complex pin pattern? Have…

• 6 min read
IC package design , APD , package design , Allegro Package Designer , SiP Layout , substrate design tools

Breakfast Bytes

Tensilica Has Its Own Track at CDNLive Silicon Valley

Tensilica products are a bigger business than many people realize. The product line…

• 2 min read
IP , CDNLive , processor , Tensilica , Xtensa , DSPs

Breakfast Bytes

DVCon Keynote: the Past and Future of Verification

Last week was DVCon, the design and verification conference. Despite the D standing…

• 5 min read
SystemVerilog , Wally Rhines , formal , Verilog , Emulation , DVcon , Rhines , simulation , verification

Breakfast Bytes

EDA in the Cloud: Stormy Weather

SoC design groups don't do clouds. True, they take advantage of some of the underlying…

• 4 min read
security , EDA , cloud , Breakfast Bytes , cloud computing

Whiteboard Wednesdays

Whiteboard Wednesdays - Reusable Data-Driven Verification Using TLM 2.0

In this week's Whiteboard Wednesdays, Zeev Kirshenbaum describes a method for creating…

• less than a min read
SystemVerilog , Verification IP , Whiteboard Wednesdays , TLM 2.0 , data driven verification

System, PCB, & Package Design 

What's Good About the Latest PSpice? The 16.6-2015 Release Has Several New Enhancements…

The 16.6-2015 PSpice release has several new features and capabilities: VBIC Support…

• 2 min read
Allegro 16.6 , AMS simulator , 16.6 , PSPICE , PCB design , AMS simulation , Grzenia

Breakfast Bytes

Turing Award; Google's First Crash

Turing Award 2016 The highest award in computer science, sometimes referred to…

• 3 min read
rsa , public key cryptography , turing award , google car , cryptography , turing , alan turing , diffie helman

SoC and IP

The most powerful feature of USB Type-C – Power Delivery

One thing that all mobile electronics devices have in common is that they all need…

• 1 min read
USB 3.0 , Jacek Duda , Consumer Electronics Show , CES , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Breakfast Bytes

Automatic Testbench Assembly

Every so often there is a change in the level where design gets done and, thus, a…

• 4 min read
automatic testbench assembly , uvm , IP-XACT , VIP , Socrates , ARM , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—PCIe Gen4: Is It Coming Anytime Soon?

In this week's Whiteboard Wednesdays video, Moshik Rubin discusses the history of…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , interfaces , PCIe , PCI Express

Breakfast Bytes

embedded world: Baby You Can Drive My Car

embedded world is a large conference held every February in Nürnberg, Germany (about…

• 5 min read
ECU , Automotive Ethernet , autonomous cars , Tensilica , Embedded World

SoC and IP

See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+

Did you miss DesignCon this year? If so, you also missed the demonstration of our…

• less than a min read
DesignCon , PCIe Gen4 , pcie4 , SerDes

Breakfast Bytes

Barcelona MWC: Cadence, Vision, Audio, USB Type-C

Cadence has been at Mobile World Congress all week. Actually they are still there…

• 4 min read
lumia , USB Type-C , mwc16 , Mobile World Congress , HiFi , convolutional neural network , MWC , Tensilica , CNN

Academic Network

Students from University of Calgary Visit Cadence Headquarters

The Cadence Academic Network is also a career network. We love to help students from…

• 2 min read
university , Cadence Academic Network , Calgary , engineering , university program
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