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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Digital Design

When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi…

Maximizing the usage of Multi-cut vias by the router is one key to improving yield…

• 2 min read
EDI , EDI system , 28nm , EDI 11.1 , NanoRoute , encounter , via , digital , Digital Implementation , multi-cut via insertion , Brian Wallace , EDI 11 , DFM , "SoC-Encounter"

Analog/Custom Design

Things You Didn't Know About Virtuoso: Change is Here to Stay

Speaking of variation -- and isn't everyone these days -- something strikes me in…

• 4 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Analog Simulation , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , variability , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Variation , IC 6.1.4 , Custom IC Design , change

System, PCB, & Package Design 

What's Good About Selection Filters in DEHDL? The Secret's in the 16.5 Release!

In the 16.5 release of Design Entry HDL (DEHDL) -- Cadence Online Support access…

• 1 min read
PCB , DEHDL , selection filters , property changes , Allegro 16.5 , Design Entry HDL , design , PCB design , 16.5 , Design Entry , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro

Verification

Trying to Make Sense of the Chaos – Impressions from Design West 2012

Walking the show floor of "Design West," the show formerly known as "Embedded Systems…

• 3 min read
SysML , Intel , Embedded Systems Conferences , software development tools , chaos , OS , embedded software , UML , Test , Design West , software , ARM , embedded systems , operating systems

Analog/Custom Design

DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups

On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference…

• 2 min read
SystemVerilog , coverage , covergroups , Functional Verification , analog , Mixed-Signal , DVcon , real number types , functional coverage , mixed signal , floating point , mixed-signal verification , verification , real number

System, PCB, & Package Design 

What's Good About PCB SI Signal Integrity Bus Analysis? Allegro 16.5 Has a Few New…

Address Bus Topology Support Part of the setup for Bus Analysis in Allegro PCB SI…

• 2 min read
PCB SI , PCB , SI , diff pairs , Signal Intregrity , SI bus analysis , SigXP UI , PCB Signal and power integrity , "PCB SI" , Allegro 16.5 , SPB , Signal Integrity , PCB Signal integrity , Allegro PCB SI , PCB design , SPB16.5 , differential pairs , SI analysis and modeling , Differential Pair Support , Allegro

Verification

Video: PSL and SVA for SPICE – Yes, Assertion Based Verification (ABV) for Analog…

In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background…

• less than a min read
Joe Hupcey III , ABV , video , SVA , Virtuoso , PSL , DVcon , assertions , Don O'Riordan , SPICE

Verification

CDNLive Silicon Valley 2012: Much More than Moore

Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley…

• 3 min read
ARM Techcon , uvm , Joe Hupcey III , ABV , CDNLive , metric driven verification (MDV) , TSMC , Lip-Bu Tan , UVM ML , apps , Lego , assertions , CDNLive! , robot , CDNLive Silicon Valley , ARM , Rubik's Cube , IFV

System, PCB, & Package Design 

What's Good About APD’s Symbol Editor App Mode? You’ll Need the 16.5 Release to See

In an IC package design, it is common for the designer to customize the BGA component…

• 5 min read
PCB , IC Packaging and SiP Design , application mode , I/O , IC Packaging , packaging , symbol editor , Allegro 16.5 , SPB , IC/package co-design , Allegro Package Designer , advanced package designer , design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

Video: Oski Dares You to Challenge Their Formal & Assertion-Based Verification Skills…

I've seen a lot of intriguing promotions over the years, but at DAC 2012 June 3-7…

• less than a min read
DAC , Joe Hupcey III , ABV , Formal Analysis , formal , Vigyan Singhal , Oski Technology , IEV

Digital Design

Collaboration, Concurrency, and Convergence: CDNLive! Silicon Valley 2012

I was out in San Jose last week for CDNLive! Silicon Valley 2012 -- our US user's…

• 3 min read
Encounterer Digital Implementation System , Digital Implementation , CDNLive!

Digital Design

Getting Started with EDI 11 – Be Aware of OS and Design Import Changes So Your Migration…

Hello, and welcome to my first blog! As an application engineer in customer support…

• 2 min read
OS , EDI 11.1 , Migration , design import , encounter , Redhat , Digital Implementation , Encounter Digital Implementation , Brian Wallace , EDI 11

System, PCB, & Package Design 

What's Good About Allegro GRE Embedded Component Support? It’s in the 16.5 Release

Just a quick post today … The Allegro Global Route Environment ( GRE ) has been enhanced…

• less than a min read
PCB , PCB Layout and routing , embedded components , global route , Routing , layer stacks , High Speed , Allegro 16.5 , SPB , PCB Editor , High-Density Interconnect , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , GRE , HDI , Allegro

Verification

Photo Essay, Video Playlist, and Comments on DVCon 2012

In addition to the annotated image gallery (click here or on the image), or the playlist…

• 3 min read
NextOp , uvm , Low Power , Joe Hupcey III , ABV , videos , Yunshan Zhu , Functional Verification , Formal Analysis , ABVIP , video , formal apps , Vigyan Singhal , Chris Komar , Oski Technology , UCIS , DVcon , assertion synthesis , robot , Assertion-Driven Simulation , Formal verification , Assertion-based verification

Digital Design

Five-Minute Tutorial: Selective Blockage In EDI 11

Today I'd like to highlight one of the new features in Encounter Digital Implementation…

• 1 min read
selectiveBlockage , EDI , EDI 11.1 , Encounter Digital Implementation11 , encounter , setPlaceMode , selective blockage , five minute tutorial , EDI 11 , placement blockage

Verification

DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Ap…

In this interview Product Engineer Chris Komar recaps the tutorial on formal apps…

• less than a min read
Low Power , Joe Hupcey III , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , formal apps , Chris Komar , DVcon , apps , assertion synthesis , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Analog/Custom Design

Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley…

• 2 min read
real number modeling , APS , Low Power , mixed signal design , CDNLive SV 2012 , parasitic , IC 6.1 , AMS Designer , CPF , analog , Mixed-Signal , analog behavoral , Virtuoso , RNM , CDNLive! , mixed signal , simulation , verification

RF Engineering

Guidelines for Maximizing Speed vs. Accuracy in SpectreRF simulations - Part 3

Several months ago, I started a 3 part series on Guidelines for Maximizing Speed…

• 4 min read
RF , RF Simulation , analog/RF , Circuit simulation , RFIC , QPSS Analysis , shooting newton , HB , Spectre RF , spectre spectreRF , Analog Simulation , MMSIM , RF spectre spectreRF , harmonic trimming , spectreRF , RF design , harmonic balance , mixer

System, PCB, & Package Design 

What's Good About Allegro PCB Router Staggered Via Rules? See for yourself in 16

Just a quick blog today on a new 16.5 Allegro PCB Router enhancement for Staggered…

• 1 min read
PCB , PCB Layout and routing , global route , Routing , staggered vias , Allegro 16.5 , via rules , PCB Editor , Layout , vias , PCB design , SPB16.5 , Allegro PCB Editor , Allegro
CDNS - Fix Layout Hompage