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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Breakfast Bytes

What's For Breakfast? Video Preview March 6th to 10th 2017

https://youtu.be/ygs0CEZXtAI Coming from Mobile World Congress, Barcelona,…

• less than a min read
gsma , Mobile World Congress , silicon photonics , netflix , mobile carriers , mobile , irps , GlobalFoundries , reliability , formula e

Breakfast Bytes

Protium: Next Generation FPGA Prototyping

FPGA prototyping is a very attractive tool for some aspects of verification. Apart…

• 5 min read
palladium z1 , Protium , FPGA prototyping , xilinx , protium s1 , FPGA

Breakfast Bytes

Xcelium: Parallel Simulation for the Next Decade

This morning, Cadence announced two new products in the verification space: Xcelium…

• 4 min read
SystemVerilog , RTL simulation , Verilog , rocketsim , xcelium , simulation

Academic Network

2nd Tensilica Day in Hanover: AR, IoT, Automotive. Pick What You Like

After the successful Tensilica Day at Hanover University last year ( presentations…

• 2 min read
hololens , Cadence Academic Network , IoT , Espressif , Tensilica , ADAS

Analog/Custom Design

Virtuoso Video Diary: Why Should you Switch to the Expression Builder for Creating…

Here’s how you can create expressions using the Expression Builder in 4 easy steps…

• 6 min read
Analog Design Environment , ADE Explorer , Analog Simulation , expressions , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design , calculator , ADE Assembler

Breakfast Bytes

DesignCon and Target Impedance

I was DesignCon recently. It is a bit of a weird conference, since it covers a wide…

• 3 min read

Breakfast Bytes

Mobile World Congress: Hololens and More

From February 27th to March 2nd it is Mobile World Congress (MWC) in Barcelona, Spain…

• 2 min read
barcelona , Mobile World Congress , Tensilica , #mwc17

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2017

https://youtu.be/RIkl4O5Q-V4 Coming from inside the Intel Museum, Santa Clara…

• less than a min read
Intel , spie advanced lithography , law enforcement , DVcon , mobile , privacy , intel investor day , stingray

SoC and IP

Three New Memory Trends in Enterprise Data Centers

You might have seen the graph below about the increase in monthly internet traffic…

• 5 min read
Design IP , Memory , DDR4 , flash , memory IP , DDR , memories

Digital Design

Making Hardware Design Great Again in 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Breakfast Bytes

Putting a Rocket Under Incisive

When Cadence first acquired RocketSim, I wrote a post, Omnia Simulation in Tres Partes…

• 3 min read
SystemVerilog , Incisive , Verilog , rocketick , rocketsim , simulation

Whiteboard Wednesdays

Whiteboard Wednesdays - Memory Models Runtime Control

In this week's Whiteboard Wednesdays video, Dharini SubashChandran explains how to…

• less than a min read
runtime , Whiteboard Wednesdays , IP , memory IP , Dharini SubashChandran

Breakfast Bytes

Cat-NB1 and HaLow Wireless Links Powered by Tensilica Fusion F1

A generic Internet of Things (IoT) device consists of some sensors, some computations…

• 4 min read
tensilica fusion f1 , tensilica fusion , tensilica f1 , Tensilica , narrowband , nb-iot , commsolid

Verification

What Sort of Bugs Does Portable Stimulus Find?

In a recent blog post , we discussed some general concepts of bugs, problems, issues…

• 3 min read
hardware-software co-verification , uvm , Low Power , pswg , debug , Functional Verification , System Design and Verification , embedded software , Emulation , Accellera , Hardware/software co-verification , debugging , portable stimulus , interrupts

Breakfast Bytes

Neural Networks and the Future

The Panel Session The recent embedded neural network symposium held at Cadence…

• 8 min read
deep learning , enns , neural networks , autonomous vehicles , debugging

Breakfast Bytes

Chris Rowen: Neural Networks—The New Moore's Law

In addition to being the master of ceremonies for the recent embedded neural network…

• 3 min read

Breakfast Bytes

Kunle Olukotun: Scaling Machine Learning Performance

The keynote at the recent Embedded Neural Network Symposium held recently at Cadence…

• 5 min read
buckwild! , Delite , plasticine , hogwild! , neural networks

Whiteboard Wednesdays

Whiteboard Wednesdays - Coherent Interconnect Verification Challenges

In this week's Whiteboard Wednesdays video, Nimrod Reiss discusses the challenges…

• less than a min read
Verification IP , Whiteboard Wednesdays , throughput , VIP , latency , snoop filtering , Nimrod Reiss , interconnect verification

Breakfast Bytes

Jeff Bier: When Every Device Can See

Jeff Bier is the founder of the Embedded Vision Alliance, which runs the annual Embedded…

• 3 min read
deep neural network , deep learning , Embedded Vision Alliance , machine learning , neural network , machine vision
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