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Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network
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Blog - Post List

Latest blogs

Digital Design

Library Characterization Tidbits: Rewind and Replay

A recap of the blogs published in the Library Characterization Tidbits blog series…

• 3 min read
Liberate AMS , Liberate LV , RAK , Liberate Variety , library characterization , Application Notes , Liberate MX , training bytes , Library Characterization Tidbit , Liberate Characterization Portfolio

System, PCB, & Package Design 

BoardSurfers: Five Easy Steps to Create Footprints Using Packages in Library Cre…

In my previous blog , I talked about creating a footprint using an existing template…

• 2 min read
Library Creator , PCB Editor , 17.4-2019 , ECAD-MCAD Library Creator , PCB design

Breakfast Bytes

Bringing Clarity of Signal to High-Performance Connector Design

I recently wrote a white paper on Signal Integrity for 112G, which I'll post about…

• 5 min read
return loss , Signal Integrity , crosstalk , clarity

Analog/Custom Design

Virtuosity: Concurrently Editing a Hierarchical Cellview

This blog discusses key features of concurrently editing a hierarchical cellview…

• 2 min read
concurrent edit hierarchical subcell , concurrent layout editing , ICADVM18.1 , concurrent editing , CLE , concurrent hierarchical editing , Custom IC Design , Virtuoso Layout Suite , Custom IC , Layout Editing

Breakfast Bytes

HiFi DSPs - Not Just for Music Anymore

When the Tensilica HiFi DSP family was first created, the focus was all on low-power…

• 4 min read
hifi 5 , Audi , HiFi , Tensilica , tensorflow lite

Whiteboard Wednesdays

Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis

In this week’s Whiteboard Wednesdays video, Dave Apte explains the flow from a TensorFlow…

• less than a min read
High-Level Synthesis , Whiteboard Wednesdays , TensorFlow , Stratus

System, PCB, & Package Design 

IC Packagers: Time-Saving Alternatives to Show Element

In the Allegro back-end layout products like Allegro Package Designer Plus, it would…

• 6 min read
Allegro Package Designer , Allegro PCB Editor

Breakfast Bytes

The Furthest Man Has Been from Earth

What is the furthest that man has been from Earth? And who? If I tell you that today…

• 4 min read
Apollo , space

Analog/Custom Design

Virtuoso Meets Maxwell: Keeping Things Simple in the Virtuoso RF Solution

We have all heard the sayings “Less is more” and “Keep it simple”. Electromagnetic…

• 5 min read
EM Analysis , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , RF design , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

John Park Webinar: Is It the Age of the Chiplet?

I first started paying attention to 3D packaging many years ago. Every year there…

• 5 min read
FOWLP , chiplets , 3D IC , more than Moore , interposer

定制IC芯片设计

Virtuosity：回顾2019年Virtuoso ADE Product Suite 及 Virtuoso Visualization and Analys…

对于 Virtuoso®ADE Product Suite 和 Virtuoso® Visualization and Analysis 而言，2019 年是非常重要的一年…

• 2 min read
Chinese blog , Cadence blogs , ICADVM18.1 , ADE Explorer , virtuoso visualization and analysis , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler

Breakfast Bytes

Sunday Brunch Video for 12th April 2020

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: From Castles…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

极致PCB设计全流程 I 基础二：DFx规则设定

当布线过程中或者布线结束时，发现器件布局不合理，我们将进行繁琐的调整工作。对于复杂PCB，这个调整可能会占用我们整个上午的时间，甚至更久。 如果设计者在布局开始时…

• less than a min read
PCB , Chinese blog , training , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro , 专家培训

Digital Design

Joules – Power Exploration Capabilities

Several tools can generate power reports based on libraries & stimulus. The issue…

• 1 min read
Low Power , Joules , Logic Design , Power Analysis

Digital Design

Exploring Genus-Joules Integration is just a click away!!

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize…

• less than a min read
Low Power , Genus , Joules , Logic Design , Power Analysis

Breakfast Bytes

Designing Chips for Hyperscale Data Centers: Tools

Yesterday's post, Designing Chips for Hyperscale Data Centers: IP , covered the high…

• 5 min read
cloud , cadence cloud , datacenter

Digital Design

Genus Synthesis Solution – Introduction to Stylus Common UI

The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus…

• 1 min read
Genus , Logic Design , common , stylus

Breakfast Bytes

Designing Chips for Hyperscale Data Centers: IP

Last week I wrote two posts about the progression from the first commercial computers…

• 5 min read
Design IP , IP , datcenter , Ethernet , 112g , SerDes

Digital Design

Quantus' Substrate Noise Analysis Functionality: RF Spurs Impacting Your Performance…

Is there anything called pindrop silence? Oh yes, I experienced the sound of silence…

• 3 min read
5G , RF , Smart View , SNA , extracted view , Virtuoso , Spectre , qrc , Liberate , signoff , Quantus
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