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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Sunday Brunch Video for 14th July 2019

https://youtu.be/HO3cViPU6Mw Made at Slovensky Raj, Slovakia (camera Gary Bengier…

• less than a min read
sunday brunch

Breakfast Bytes

The Mercedes Benz Museum and the Invention of the Automobile

Recently, I was in Stuggart, Germany. This is the home to the headquarters of both…

• 5 min read
Automotive , mercedes benz

PCB、IC封装：设计与仿真分析

Cadence LPDDR4设计IP通过TSMC 16FFC FinFET 车规工艺验证

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“ Cadence Memory IP for LPDDR4…

• less than a min read
PCB , SI , Chinese blog , 仿真分析 , LPDDR4 , 中文 , Sigrity , 信号完整性

Analog/Custom Design

Virtuosity: Device-Level Routing for Advanced Nodes – Using Generate Trunks

The Trunk Generation feature is the founding piece that offers incremental productivity…

• 2 min read
Trunk generation , Interactive Routing , Pin to Trunk , ICADVM18.1 , Virtuoso Space-based Router , Layout EXL , Layout Suite , trunk creation , Virtuoso , Generate Trunk , EM Trunk Optimization , Custom IC Design , space based router , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

NXP: Can Silicon Valley Really Crack the Automakers' Code?

The second panel at the recent NXPConnect was about Silicon Valley versus traditional…

• 7 min read
Automotive , NXP , ADAS

Computational Fluid Dynamics

VPLP Design: Revolutionizing Hydrofoil Design with Advanced CFD Simulation Techn…

Hydrofoils have unleashed the speed of sailing boats since the last two America’s…

• 4 min read

定制IC芯片设计

Virtuosity: 过滤波形

在接下来的几周内，Virtuosity和Virtuoso Video Diary博客将重点关注 Virtuoso®ADE Assembler , Virtuoso…

• less than a min read
Chinese blog , ADE Explorer , plotting , plot , Filtering , ViVA , Virtuosity , ADE Blog Series , Custom IC Design , ADE Assembler

Breakfast Bytes

Carry: Electronics

The last two days I have written about carry in mechanical calculating devices. See…

• 7 min read
carry , adder

Whiteboard Wednesdays

Whiteboard Wednesdays - Cloud-Hosted Design Solution – a Full-Service Cloud Offe…

In this week's Whiteboard Wednesdays video, Jeff Critten describes the key benefits…

• less than a min read
Cloud-Hosted Design , Whiteboard Wednesdays , cadence cloud

Verification

AMBA Adaptive Traffic Profiles: Addressing The Challenge

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components…

• 4 min read
Adaptive Traffic Profiles , Performance modeling , AMBA , ATP

System, PCB, & Package Design 

BoardSurfers: Look Before You Leap - Verifying Footprints in the Design Capture …

View the footprints of symbols during design entry in Capture: verify the footprint…

• 2 min read
Capture CIS , PCB Editor , footprint viewer

System, PCB, & Package Design 

IC Packagers: Balance Your Designs with Cadence SiP Layout

As designs get more complicated, package substrates are seeing more silicon-driven…

• 8 min read
IC Packaging , APD , SiP Layout

Breakfast Bytes

Carry: Babbage's Engines

Yesterday's post Carry: From Logarithms to Mechanical Calculators talked about how…

• 4 min read
carry , analytical engine , difference engine , Babbage

定制IC芯片设计

Virtuoso视频日记：创建和预览激励

在接下来的几周内，Virtuosity和Virtuoso视频日记博客将重点关注 Virtuoso® ADE Assembler , Virtuoso® ADE Explorer…

• less than a min read
Chinese blog , ADE Explorer , stimuli form , stimuli , Virtuoso Analog Design Environment , ViVA , Virtuosity , ADE Blog Series , Custom IC Design , ADE Assembler

Breakfast Bytes

Carry: From Logarithms to Mechanical Calculators

I hope you had a great July 4th long weekend if you are in the US...and if you were…

• 6 min read
carry , ripple carry

Breakfast Bytes

Sunday Brunch Video for 7th July 2019

https://youtu.be/re7U6Rg0MHA Made at Cadence charge station (camera Sean) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

IC Packagers: Vary Your Assembled Packages, Not Your Databases

Design variants are a common phenomenon, whether you design package substrates or…

• 7 min read
IC Packaging , APD , SiP Layout

Breakfast Bytes

Off-topic: Geography

It's the day before a holiday so Breakfast Bytes goes completely off-topic as usual…

• 4 min read
offtopic

System, PCB, & Package Design 

BoardSurfers - Guest Roll: Anatomy of a Good Testcase

Rik Lee, the author of today's post, is a PCB Designer with more than 35 years experience…

• 5 min read
APD , PCB Editor , SiP Layout
CDNS - Fix Layout Hompage