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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

EU Specmaniacs: ClubTs Are Coming in 2 Weeks!

EU-based Specmaniacs and "Trailblazers" rejoice: the annual ClubT series is back…

• 2 min read
IEEE 1647 , events , IntelliGen , Low Power , Specman , HW/SW , OVM ML , metric driven verification (MDV) , Functional Verification , OVM , VIP , OVM e , Mixed Signal Verification , Multi-domain verification: HW/SW co-verification , Incisive , e , ISX (Incisive Software Extensions) , ClubT , SystemC , ESL , IES-XL , Trailblazer

Verification

Must Have Advanced Verification to Achieve Software Signoff

In a recent blog on EDA Graffiti, Paul McClellan he talks about Software Signoff…

• 2 min read
EDA Graffiti , System Design and Verification , embedded isx , software signoff

Verification

Specman 9.2 Preview: A Fresh Profile on the Profiler

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 2 min read
performance , Specman , Functional Verification , e , team specman , IES-XL

Verification

Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip…

I'm not proud to admit that I reacted with envy to the news that Twitter just received…

• 2 min read
events , Specman , CDNLive , metric driven verification (MDV) , Functional Verification , IBM , VIP , MDV techtorial , DVClub , Enterprise Manager , Enterprise Planner , team specman , DVcon , Twitter , ARM , MDV , verification , Trailblazer

System, PCB, & Package Design 

What's Good About Allegro's Component Placement Changes? - More Features in SPB16

In the SPB16.2 release of Allegro PCB Editor , there are two (2) new very helpful…

• 3 min read
SPB 16.2 , Placement Replication , Component Alignment , Allegroro , PCB design

Verification

What's the New CMO Mean For Cadence and System Design and Verification?

If you track Cadence stock or other EDA leadership news you undoubtedly know we've…

• 1 min read
ASIC , TLM , System Design and Verification , John Bruggeman , software , embedded , FPGA

Verification

Upcoming ARM Techcon3 or is it Techcon Cubed?

The annual ARM Developers' Conference has been renamed ARM techcon3 , or maybe it…

• less than a min read
techon3 , Cypress , ARM , ESL , System Design and Verification

Verification

Specman-Matlab Package Update

[Preface: we interrupt the Specman 9.2 Preview series to notify you of an update…

• 3 min read
Specman , Functional Verification , C , e , Incisive Enterprise Simulator (IES) , ESL , Matlab , IES-XL

Verification

Back to School and Back to the Embedded Software Challenge

The kids have a week of school in the rear view mirror and it's time to get back…

• 3 min read
DAC , System Design and Verification , virual platform

Analog/Custom Design

Things You Didn't Know About Virtuoso ADE

After delving into lots of new features in the Virtuoso Schematic Editor, the Library…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

System, PCB, & Package Design 

What's Good About Eye Masks in PCB SI? You'll Need SPB16.2 to See!

Eye masks let you specify the acceptable parameters for what an eye should look like…

• 3 min read
SPB 16.2 , Signal Intregrity , SigWave , Allegroro , PCB design

Verification

Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

Since your circuit always runs at low-power, your verification should too. To get…

• 2 min read
funtional verification , CPF , Low-Power , Incisive , IES

Verification

Requirements for a Student Version of Specman/IES-XL?

Allow me to interrupt my blogging on MarCom and DAC to pose a question inspired by…

• 1 min read
SystemVerilog , Specman , Functional Verification , student version , Incisive , e , SystemC , Incisive Enterprise Simulator (IES) , IES-XL

System, PCB, & Package Design 

What's Good About Split Parts in AMS Simulator? More Features in SPB16.2!

This new SPB16.2 feature allows Allegro AMS Simulator (PSpice) customers to simulate…

• 1 min read
SPB 16.2 , Allegroro AMS Simulator (PSpice) , PCB design , Allegro

Verification

Specman 9.2 Preview: Shortened “When Subtype” Declarations

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 2 min read
Specman , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Digital Design

Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects

Have you ever gotten to signoff DRC and found that there was a small area where a…

• 2 min read
power vias , filler cells , highlighted objects , checkFiller , 8.1 , Digital Implementation , verifyPowerVia , "SoC-Encounter" , F9

Verification

Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

Does the union of verification automation and IT+source code management tools get…

• less than a min read
DAC , Tivoli , metric driven verification (MDV) , Functional Verification , IBM , Enterprise Manager , Enterprise Planner , MDV , Rational , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Functional Verification and EDA "Startups"

A few weeks before DAC, I started working on a blog post about the number of small…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM , System Verification , verification

Analog/Custom Design

Things You Didn't Know About Virtuoso: RTFM

Wait, don't run away! In this case I really mean " Read The Fantastic Manual ". A…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design
CDNS - Fix Layout Hompage