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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Focus Area: EDA Librarians - Manual Versus Automatic

Nope - I'm not talking about automobile transmissions ... I'll continue my series…

• 2 min read
SPB 16.2 , Library and design data management , APutomatic , PCB design , Librarians

Verification

Tech Pubs Tips Series Kickoff: Search for Single Character Words

[Team Specman welcomes the Technical Publications Team to our blog] Effectively documenting…

• 1 min read
Specman , C , e , Enterprise Manager , Incisive Enterprise Simulator (IES) , IES

Analog/Custom Design

Your Virtuoso MMSIM Portfolio 2009 Performance Outlook

John Pierce, Product Marketing Director for Virtuoso Simulation application gives…

• 1 min read
mixed-signal simulators , Chip-level simulation , MMSIM , Virtuoso IC 6.1.3 , Block-level simulation , RF design , AMS simulation , Circuit Design , Simulators , Custom IC Design , custom design technology

Digital Design

Constraint Construction: What's Its Function? Part 1 of 4

Have you found yourself frustrated at the lack of some decent timing constraints…

• 3 min read
Constraint Design , SoC-Encounter , Digital Implementation forums , SoC-Encounter 8.1 , 8.1 , Digital Implementation , Encounter Digital Implementation , Encounter Timing System , "SoC-Encounter"

SoC and IP

Memory's Recession: Actions and Realities

Now is the Winter of our Discontent: Five months into a memory industry recession…

• 7 min read

Digital Design

Programmatically Troubleshooting Timing Violations With "report_timing -collection…

Has something like the following ever happened to you? You've placed and optimized…

• 4 min read
Static timing analysis , CTE-TCL , Digital Implementation , scripting , tcl

Digital Design

How to Create a Repeating Power Switch Pattern with addPowerSwitch

I mentioned in my last post that I'd been having lots of fun with power switches…

• 2 min read
Low Power , Digital Implementation , addpowerswitch

Verification

Tech Tip - Double Wall Clock Performance with One Easy Step

[Please welcome guest blogger Silas McDermott, an Application Engineer in our Field…

• 2 min read
Specman , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Verification

Scalable OVM Register and Memory Package

Drawing on nearly a decade of experience, Cadence has just posted the first release…

• 2 min read
SystemVerilog , OVM , vr_ad , Register Package , e , eRM

Verification

Of EDA Vendors and Conferences

There's an interesting thread on Cool Verification ( http://www.coolverification…

• 1 min read
Functional Verification

System, PCB, & Package Design 

Brad Griffin Speaks at DesignCon - Give Him a Listen!!

If you were not lucky enough to be atDesignCon this week, and many of us were not…

• less than a min read
PDN , cadence , Digital SiP design , Advanced Node , IC Packaging & SiP design , SerDes , IC design , IC Package Physical layout and co-design , design chain

System, PCB, & Package Design 

What's Good About ASA Differential Pair Swapping? - The Secret's in the SPB16.2 Release

And the new features list just keeps going on and on - it's terrific! In the SPB16…

• 1 min read
SPB 16.2 , ASA , PCB design , differential Pair Swapping , Allegro

Verification

Exploring the Virtual Platform Part 3

Welcome to part 3 of the "Exploring the Virtual Platform" series. For readers just…

• 4 min read

Analog/Custom Design

Virtuoso Advanced Parallel Simulation Leveraging Parallelization Technology.

There is an interesting interview with Nebabie Kebebew, Sr. Product Marketing Manager…

• less than a min read
mixed-signal simulators , Chip-level simulation , MMSIM , Block-level simulation , Virtuoso , AMS simulation , Circuit Design , Simulators , Custom IC Design , custom design technology

Verification

Report From DesignCon 2009

This week the " DesignCon " show is in town (<= 10 minutes from the Cadence campus…

• 2 min read
DesignCon , Functional Verification

Verification

Good Article Alert: End "EDA Bashing"

Allow me to direct your attention to a most welcome article in EDA DesignLine written…

• less than a min read
Functional Verification , edadesignonline , EDA

SoC and IP

Web Survey: LP DDR and DDR3 DRAMs

LP DRAMs and PC DDR3 DRAMs: Vendors’ Portfolios Fill out Slowly (LP) and Rapidly…

• 3 min read

Verification

Incisive Software Extensions (ISX) vs Co-Verification Link (CVL)

Team Specman has been doing a great job supplying nifty tech tips and other useful…

• 3 min read
CVL , Co-verification link , System Design and Verification , Specmen , Incisive Software Extensions , ISX

Verification

Linking C and e: The Co-Verification Link

[Join Team Specman in welcoming guest blogger Jason Andrews. Jason is a recognized…

• 3 min read
Specman , HW/SW , C , e , ISX , Incisive Enterprise Simulator (IES) , Jason Andrews , IES
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