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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About ADW’s Design Migration? 16.6 has many new enhancements!

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required…

• less than a min read
Allegro 16.6 , cadence , 16.6 , Allegro Design Workbench , design data management , design , Grzenia , library , ADW , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 8, Many Ways to Sum a List (Closures -- Functions with…

In the past several postings to this blog, we've looked at various ways to sum a…

• 8 min read
Team SKILL , lexical closures , programming , Jim Newton , closures , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

Verification

Develop For Debugability – Part II

Looking at Coding Styles for Debug In this blog post we are going to discuss 3 different…

• 3 min read
AF , Specman , Specman/e , debug , Functional Verification , debugability , debuggability , e language , Incisive Enterprise Simulator (IES) , Daniel Bayer

System, PCB, & Package Design 

What's Good About FSP’s Design Compare? Check Out 16.6!

The 16.6 Allegro FPGA System Planne r (FSP) product has an extremely helpful Design…

• 2 min read
PCB , PCB Layout and routing , Allegro 16.6 , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , Taray , FPGAs , SPB , PCB Editor , Design Entry HDL , Layout , design , FSP , PCB design , Grzenia , comparing constraints , FPGA , Allegro , FPGA: PCB

Digital Design

Answers to Top 10 Questions on Performing ECOs in EDI System

Applying ECOs to a design can be complex, stressful and error prone so it's important…

• 6 min read
ECO , Cadence EDI System , LEC , encounter digital implementation system , tips and tricks , Synthesis , mmmc

System, PCB, & Package Design 

What's Good About DEHDL’s Constraints Comparison? The Secret's in the 16.6 Release

The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare…

• 2 min read
PCB , Allegro Design Entry , Constraint-driven PCB Design flow , constraint databases , Allegro 16.6 , 16.6 , property , PCB Editor , Constraint Manager , Layout , design , constraint difference , PCB design , Grzenia , Schematic , Allegro

Analog/Custom Design

Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support

Topics in March include advanced analysis in ADE GXL, taking advantage of lots of…

• 2 min read
Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , Rapid Adoption Kit , IC615 , IC 6.1.5 , ADE , VLS GXL , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso Layout Suite L , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , VLS L , AMS simulation , Custom IC Design , modgens , RAKs , Virtuoso Layout Suite , Virtuoso Layout Suite GXL , VLS XL , SKILL , Virtuoso Layout Suite XL

System, PCB, & Package Design 

Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP

The level of ease and efficiency you experience in selecting the items needed for…

• 2 min read
package , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , APD , wirebonds , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , wirebonding , IC Package Physical layout and co-design

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself…

Beginning with the Allegro PCB Edito r 16.6 release, you are provided a methodology…

• 2 min read
PCB , PCB Layout and routing , ECSets , Constraint-driven PCB Design flow , constraint databases , Allegro GUI , Allegro 16.6 , electrical constraints , 16.6 , SPB , PCB Editor , Constraint Manager , Layout , design , "PCB design" , constraint difference , PCB design , Constraints , Grzenia , Allegro PCB Editor

Verification

Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding…

• 4 min read
AF , Specman , debug , Functional Verification , encapsulate , aspect-oriented programming , encapsulating aspects , debugability , e language , Incisive Enterprise Simulator (IES) , debugging , simulation , verification , Daniel Bayer

System, PCB, & Package Design 

What's Good About RF PCB and Autoplace? 16.6 Has Many New Enhancements!

The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over…

• 5 min read
PCB , PCB Layout and routing , RF , Cadence Design Systems , Allegro RF SiP , Allegro 16.6 , RF PCB , autoplace , 16.6 , Placement Edit , SPB , PCB Editor , Design Entry HDL , design , PCB design , Design Entry , Grzenia , Allegro PCB Editor , Schematic

Analog/Custom Design

Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two…

• 2 min read
AMS , EDI , CDNLive , CDNLive 2013 , MS ToT , cadence , tech on tour , mixed-signal IP , AMS Designer , analog , analog behavioral models , analog/mixed-signal , Virtuoso , mixed signal methodology guide , mixed signal , CDNLive SV 2013 , OpenAccess , SoCs , AMS Verification , mixed-signal verification

Digital Design

Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Ana…

When running power and rail analysis for a flip chip, we used to have to spend some…

• 3 min read
EDI , rail analysis , EPS , Five-Minute tutorial , Power Analysis , flip chip , bump

Verification

Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of…

Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes…

• 2 min read
SystemVerilog , IDA: Functional Verification , ACE , Specman , Specman/e , cadence , debug , Specman e , Incisive Enterprise Simulator , Incisive Debug Analyzer , EDA , Incisive , e , Incisive Enterprise Simulator (IES) , simulation , IUS , EE Times

System, PCB, & Package Design 

What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements!

In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more…

• 5 min read
PCB SI , PCB , SI , inset vias , Allegro 16.6 , cadence , Signal Intregrity , SigXP UI , 16.6 , PCB Signal and power integrity , layer stacks , "PCB SI" , Signal Integrity , via , design , "PCB design" , Design Reuse , PCB Signal integrity , Allegro PCB SI , Grzenia , SI analysis and modeling , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 7, Many Ways to Sum a List

In this episode of SKILL for the Skilled I'll introduce a feature of the let primitive…

• 4 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for 16.6…

Perhaps the most time-consuming aspect to designing the package substrate for a large…

• 1 min read
IC Package , IC Packaging , Digital SiP design , Advanced Package Router , 16.6 , IC Packaging and SiP , APR , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , IC Package Physical layout and co-design

System, PCB, & Package Design 

Customer Support Recommended – Regulation Loop Design Using Allegro AMS Simulator…

Feedback regulation loops are widely used by power electronic designers. It is one…

• 3 min read
SPB16.3 , Allegro 16.6 , customer support , AMS simulator , closed loop design , 16.6 , Allegro 16.3 , Support , Allegro AMS , Allegro 16.5 , PSPICE , Appnotes , loop design , regulation loops , Appnote , feedback regulation loops , "PCB design" , open loop design , PCB design , 16.5 , AMS simulation , SPB16.5 , application note , Schematic

System, PCB, & Package Design 

What's Good About Allegro Package Designer (APD) Bond Wire "Text In?" You’ll Need…

Cadence IC Packaging tools today provide a spreadsheet-based import mechanism for…

• 2 min read
PCB , IC Packaging , Allegro 16.6 , cadence , 16.6 , APD , Wirebond , Allegro Package Designer , design , bond wires , Grzenia , die abstract , wire bond , Allegro
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