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Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction…

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems…

• 3 min read
time-to-market , High-Level Synthesis , verification turnaround , TLM , C-to-Silcon , ROI , System-Level Design , SystemC , C-to-Silicon Compiler , productivity

Digital Design

Encounter Quick Tip: Dimming the Display with F12

I remember when I first started working with the Cooper & Chyan Technology (CCT)…

• 1 min read
dimming display , Encounterer Digital Implementation System , highlight , display , encounter , highlighted objects , darken display , quick tip , F12

Analog/Custom Design

Managing ECOs in Mixed Signal Designs

Imagine you are days away from completing the implementation of a fairly complex…

• 3 min read
ECO , Farhat , mixed signal design , CPF , Open Access , Floorplanning , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , Mixed signal physical implementation

Verification

Amazon’s New Kindles: More Steps Toward the Paperback Computer

While I understand that a new Kindle Fire at $199 MRSP is significantly more than…

• 4 min read
Verification IP , RPP , SaaS , Joe Hupcey III , paperback computer , Cadence VIP portfolio , Kindle , system realization , VIP , EDA360 , EDA , VSP , Palladium XP , tablet , Hosted Design Solutions , Jim Hogan , Rapid Prototyping Platform , Amazon , Steve Leibson , cloud computing

Digital Design

Encounter Quick Tip: Finding Available Cell Masters with dbGet

When you first start using dbGet, many of your queries branch off the "top" keyword…

• 1 min read
dbGet , finding cells , cell masters , filler cells , encounter , Digital Implementation , Encounter Digital Implementation , quick tip

Verification

Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several…

• 2 min read
IntelliGen , Specman , Incisive Enterprise Simulator , Incisive , e , SVA , e language , team specman , OOP , assertions , eRM , simulation , AOP , verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Allegro Database Locking? See for Yourself in 16.5!

Prior to the SPB16.5 release, multiple designers can edit and update the same Allegro…

• 2 min read
PCB , database locking , Allegro 16.5 , SPB , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

edaForum: Evolving Devices from “All in One” to “One for All”

This week I had the pleasure to attend and to present at the 11th annual edaForum…

• 7 min read
PCB , IMC , Intel , virtual platforms , edaForum , virtual prototypes , IP integration , System Development Suite , EDA360 , embedded software , Shirrmeister , IC/package co-design , one for all , hardware/software co-development , Power Analysis , System Design & Verification , Frank Schirrmeister , all in one , Eul , power , debugging , System Design and Verification

Verification

Missing Real-World Assertions in Computer-Land

I was reviewing the page view statistics on the Cadence Functional verification…

• 3 min read
uvm , ABV , outlook , Functional Verification , formal , assertions , Assertion-based verification

Verification

Virtual Platform UART Use Number 3: Using gdb to Debug a Software Application

This is the next installment in my series covering the uses of the venerable UART…

• 7 min read
virtual prototoypes , virtual platforms , TLM , GDB , debug , UART , embedded software , software , SystemC , debugging , linux , System Design and Verification

System, PCB, & Package Design 

What's Good About AMS Partial Design Simulation? It’s in the 16.5 Release!

Partial Design Simulation aims at unifying the PCB and simulation flow by enabling…

• 2 min read
PCB , "capture CIS" , AMS , AMS simulator , Capture CIS , Allegro 16.5 , Allegro 16.2 , partial simulation , PSPICE , design , AMS simulation , Design Entry , SPB16.5 , PCB Capture

Verification

ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly…

• 1 min read
Verification IP , ACE , Cortex-A15 , Functional Verification , video , VIP , interconnect monitor , ACE verification , cache coherency , coherency , ARM

Verification

Tech Tip: The “Show Me” Witness Trace Short-Cut for Design Bring-Up

In a prior Team Verify post, Application Engineer Bin Ju talked about several applications…

• 1 min read
show me , ABV , Functional Verification , Formal Analysis , formal , ADS , Chris Komar , witness trace , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification

Verification

Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

Our friend and fellow blogger JL Gray recently published a post with the provocative…

• 2 min read
SystemVerilog , uvm , uvm world , universal verification methodology , UCIS , Accellera , JL Gray

System, PCB, & Package Design 

What's Good About Net Groups in Capture? Check Out the 16.5 Release and See!

A NetGroup is a collection of nets. The nets in a NetGroup can be scalar, vector…

• 2 min read
"capture CIS" , Allegro Design Entry , Capture CIS' , Design Entry CIS , OrCAD Capture Marketplace , electrical constraints , Capture CIS , Capture-CIS , Allegro 16.5 , design , OrCAD , Design Entry , net groups , SPB16.5 , NetGroup , PCB Capture , Schematic

Verification

Everything New is Old … Everything Old is New

The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl…

• 2 min read
gate level , Functional Verification , LEC , RTL , DRC , LVS , EDA , old , gate-level , new , simulation

System, PCB, & Package Design 

What's Good About ADW’s Server? 16.5 Has a Few New Enhancements!

Some of the enhancements to the Allegro Design Workbench (ADW) 16.5 release were…

• 1 min read
PCB , Allegro Design Workbench , Library flow , Allegro 16.5 , design data management , design , "PCB design" , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

Welcome to the next installment in my series about different ways to use the venerable…

• 4 min read
Virtual System Platform , TLM , virtual platform , UART , System Design and Verification , telnet , embedded software , xterm , virtual prototype , software , SystemC , linux , ESL

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 2

In the previous posting Introduction to Classes -- Part 1 we introduced the problem…

• 3 min read
Team SKILL , programming , object orientation , Virtuoso , Lisp , SKILL++ , SKILL
CDNS - Fix Layout Hompage