Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About PCB SI Model Library Management? Look to SPB16.3 and See!

The SPB16.3 release of Design Entry HDL (DEHDL) provides an easier method for setting…

• 2 min read
PCB SI , PCB , SCM , SI , SPB16.3 , Allegro Design Entry , diff pairs , Signal Intregrity , DEHDL , Allegro 16.3 , SPB 16.3 , property , Library flow , SPB , PCB Editor , Constraint Manager , ASA , Allegro System Architect (ASA) , Front-end PCB design , design , PCB Signal integrity , PCB design , Design Entry , differential pairs , SI analysis and modeling , File Directives , Differential Pair Support , ConceptHDL , dml , model editor , Schematic

Verification

Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and…

• 3 min read
SystemVerilog , Specman , OVM ML , Testbench simulation , OVM e , EDA , e , e language , team specman , Aspect Oriented Programming , eRM , simulation , AOP , Functional Verificatioa , IES-XL

Verification

Achieve the Next Level of Verification Productivity with Specman Advanced Option

Advanced verification customers are seeing their verification environments getting…

• 3 min read
Specman , Object Oriented Programming , debug , Functional Verification , Testbench simulation , e , e language , team specman , Aspect Oriented Programming , eRM , testbench , IES , AOP , verification , IES-XL , Trailblazer

Verification

In Verification, Failing to Plan = Planning to Fail

So I know you tell your kids this, you tell your spouse this, you heard it from…

• 2 min read
uvm , Verification methodology , metric driven verification (MDV) , Functional Verification , vPlan , MDV techtorial , verification planning , Incisive , Enterprise Manager , Enterprise Planner , FPGA , verification

System, PCB, & Package Design 

What's Good About APD Wire Bonding? SPB16.3 has MANY New Enhancements!

As with every new release, a primary focus for the Allegro Package Designer (APD…

• 14 min read
IC Packaging and SiP Design , SPB16.3 , IC Packaging , global route , Routing , Allegro 16.3 , layer stacks , SPB 16.3 , APD , SPB , PCB Editor , High-Density Interconnect , BGA , Layout , design , "PCB design" , PCB design

Verification

There's Another Simulation Failure! New SimVision Features Can Help

Simulation failures are seen quite often in design verification. Fortunately, with…

• 4 min read
uvm , debug , Functional Verification , simvision , Incisive , Silicon Realization

Verification

Applying Digital-Centric Verification Methodologies to Analog

A majority (if not all) SoCs today are mixed signal. Increasingly, the analog and…

• 4 min read
AMS , Low Power , Real Value Modeling , Functional Verification , Mixed Signal Verification , Mixed-Signal , metric-driven verification , SoC Connectivity , System Verification , Incisive Enterprise Simulator (IES) , IP modeling , RVM

Verification

My Reason For Choosing e – a Much More Advanced Verification Language. What’s Your…

I'd like to share with you a story from many, many, many moons ago when I first evaluated…

• 7 min read
SystemVerilog , Specman , debug , Functional Verification , e , e language , Aspect Oriented Programming , AOP

Verification

More on the Benefits of Metric-Driven Formal Analysis and Verification (MDV + ABV…

We interrupt R&D's Vinaya Singh's excellent series on "The Role of Coverage in Formal…

• 2 min read
Alok Jain , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , vPlan , corner cases , formal , EDA360 , verification planning , Coverage-Driven Verification , Enterprise Manager , intent , Enterprise Planner , Silicon Realization , coverage driven verification (CDV) , MDV , IEV , IFV , Coverage Driven Verification , verification

Verification

What Does Silicon Realization Mean for Verification Engineers?

Last May , I posed a question about what EDA360 means for verification engineers…

• 2 min read
performance , uvm , Functional Verification , vPlan , formal , OVM , VIP , EDA360 , Multi-Core , Incisive , Silicon Realization , metric-driven verification , multicore , IEV , simulation , IES , IFV

Verification

How Elastic is Your Business?

Facing a verification overrun, you poached resources, clocked overtime, and kept…

• 3 min read
Functional Verification , verification planning , profitability , business , elastic , metric-driven verification , MDV

Verification

Infinite Playbook for the Verification Superbowl

Its 4th and long, you're down by six, the clock is running out, and you are wary…

• 2 min read
SystemVerilog , uvm , debug , Functional Verification , OVM , EDA360 , Multi-Core , Incisive , Silicon Realization , Incisive Enterprise Simulator (IES) , Accellera VIP TSC , simulation , IES

Digital Design

Advanced Maneuvers in Feedthrough Insertion: Maximizing Routability while Minimizing…

Previously I wrote about the basics of feedthrough insertion in Encounter . Today…

• 2 min read
EDI system , hierarchical design , feedthrough insertion , encounter , Digital Implementation

Verification

System Realization Webinars in 2010 -- A Summary

Last year was unprecedented for Cadence. We came up with the EDA360 vision , reorganized…

• 5 min read
High-Level Synthesis , TLM , Fast Models , IP-XACT , Models , system realization , TLM 2.0 , Calypto , TSMC , Magillem , virual platform , virtual protoype , virtual prototype , Jeda , Imperas , Virtual Platforms , CircuitSutra , TLM 2.0-driven design , XtremeEDA , SystemC TLM2 , ESL , CoFluent , System Design and Verification

System, PCB, & Package Design 

What's Good About PCB SI Metal Surface Roughness? SPB16.3 Has Some New Enhancements

Happy New Year! Electromagnetic Solution 2D (EMS2D) is designed for accurate transmission…

• 2 min read
PCB SI , PCB , EMS2D , SI , RF , SPB16.3 , SiP , Signal Intregrity , Digital SiP design , SigXP UI , Allegro 16.3 , SPB 16.3 , electromagnetic , field solver , PCB design , EM , SI analysis and modeling , Allegro

Analog/Custom Design

SKILL for the Skilled: What is SKILL++?

The way SKILL++ deals with functions is a bit different than the way traditional…

• 5 min read
Team SKILL , hierarchy , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL , Allegro

Verification

How I Nearly Had My Own “Subtract Bug” in a CPU Design

In a recent blog post , I talked about learning a public lesson on the importance…

• 3 min read
divide , subtract bug , debug , Functional Verification , bugs , corner cases , Cydrome , subtract , add , verification

Verification

More on the SystemC ARM Linux Boot Loader

My last post described a Linux Loader for ARM Virtual Platforms . Taking a closer…

• 3 min read
virtual platforms , android , boot loader , SystemC , ARM , debugging , linux , kernel

Verification

The Role of Coverage in Formal Verification, Part 1 of 3

As outlined in a prior post , new advances in formal and multi-engine technology…

• 4 min read
ABV , methodology , verification strategy , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , Cadence VIP portfolio , formal , VIP , CDV , SVA , PSL , coverage driven verification (CDV) , assertions , MDV , IEV , IFV
CDNS - Fix Layout Hompage