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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

Analog/Custom Design

Virtuoso Video Diary: Run Point Selection -WYSIWYG

With Virtuoso ADE Explorer and Virtuoso ADE Assembler , it is easy to create setups…

• 4 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , Mixed-Signal , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design

Breakfast Bytes

CCIX Is Pronounced C6

Cache coherency has become a big issue as the architecture inside devices such as…

• 4 min read
GPU , ccix , cache coherency , offload processors , Breakfast Bytes , FPGA

Breakfast Bytes

Ricardo's Difficult Idea

Today is an important anniversary. It is part of the explanation of why we design…

• 5 min read
ricardo , unemployment , trade , comparative advantage , david ricardo , Breakfast Bytes , technology

RF Engineering

Noise Simulation in Spectre RF Using Improved Pnoise/Hbnoise and Direct Plot Form…

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM…

• 3 min read
HBnoise , HB , Spectre RF , pnoise , noise simulation , Virtuoso , RF design , pss

Breakfast Bytes

What's For Breakfast? Video Preview April 24th to 28th 2017

https://youtu.be/OttUOjIHJf0 Coming from the Cadence coffee bar (camera Sean…

• less than a min read
Automotive , microsoft , Raspberry Pi , CDNLive , cloud , raspberry pi zero w , EDAC , ISO 26262 , CDNLive Silicon Valley , ARM , synopsys , reliability , esd alliance , Mentor

Breakfast Bytes

Autonomous Is the New Mobile: Linley on Cars

Cars are everywhere these days. It doesn't really matter what sort of event you attend…

• 7 min read
Intel , NXP , NVIDIA , Linley , mobileye , autonomous , Qualcomm , ISO 26262 , ADAS , visionpx , Breakfast Bytes

Breakfast Bytes

We Live on a Radioactive Planet Bombarded by Cosmic Rays

We live on a radioactive planet bombarded by cosmic rays. As a result, high-energy…

• 5 min read
thermal neutrons , alpha particles , high energy neutrons , see , single event effects , Breakfast Bytes

Breakfast Bytes

Developing Fingerprint Readers for Developing World Medicine

Every aspiring 7-year old detective knows that fingerprints are unique. I actually…

• 4 min read
security , biometric , fingerprint , OrCAD , PCB design , Breakfast Bytes , simprints , Allegro

Breakfast Bytes

Retimers, Gearboxes, and the Drive to PAM4

If you listen to presentations about high-speed networking for datacenters, you will…

• 5 min read
Optical , gearbox , pam4 , fiber optic , Fiber , retimer , Ethernet , Breakfast Bytes

Breakfast Bytes

The Gargini Roadmap for Semiconductors

Paolo Gargini gave the opening keynote at GOMAC recently. It was titled The Secret…

• 10 min read
irds , Intel , paolo gargini , ITRS , gnomic , moore's law , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - USB Type-C and the 5 Barriers to New Standards

In this week's Whiteboard Wednesdays video, Tom Hackett explains why the USB Type…

• less than a min read
USB Type-C , Standards , USB

Digital Design

Let Your DRC Fly! Cadence Announces Breakthrough in SoC Physical Verification

This morning we announced our next-generation Pegasus Verification System, the biggest…

• 2 min read
Physical verification , CDNLive , pegasus , DRC , design rule check , silicon signoff

Breakfast Bytes

What's For Breakfast? Video Preview April 17th to 21st 2017

https://youtu.be/3sofRincYsg Coming from CDNLive Silicon Valley (camera Sean…

• less than a min read
ser , linley group , ccix , SDE , single event error , cache coherency , open source , see , system design enablement , ISO 26262 , ADAS , autonomous vehicles

Breakfast Bytes

Pegasus Flies to the Clouds

There is a famous line in Lewis Carrol's Through the Looking Glass that could have…

• 5 min read
pvs2 , Physical verification , pegasus , Dracula , DRC , design rule check , PVS , Assura , Breakfast Bytes

Breakfast Bytes

Six Reasons to Go to DAC—Plus One Very Big One

There are thousands of good reasons to go to DAC this year. I'll give you seven in…

• 5 min read
dac54 , Costello , Joe Costello , dac43 , keynote , Design Automation Conference , Breakfast Bytes

Breakfast Bytes

What Keeps MGM's Head of Security Up at Night? Lightbulbs!

The trusted supplier day at GOMAC opened with a slightly off-topic, but fascinating…

• 8 min read
security , mgm , target , mgm resorts international , gomac , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview April 10th to 14th 2017

https://youtu.be/nvwMIujDzco Coming from Monterey CA (camera me) Monday…

• less than a min read
irds , PCB , security , Intel , DAC , paolo gargini , dac54 , ITRS , CDNLive , linley group , Linley , cloud , fingerprint , OrCAD , retimers , gomac , datacenter , networking

Breakfast Bytes

See Further by Standing on the Shoulders of...OpenVX

For power and performance reasons, video and vision processing are attractive to…

• 5 min read
khronos , Vision P6 , Tensilica , openvx , Breakfast Bytes

Digital Design

“Great” Hardware Design in a Wireless World

As part three of the “ Making Hardware Design Great Again” series , let’s see how…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS
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