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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Thermal Effects on Voltage Margins with Celsius…

Capture the effects of temperature on electrical design margins with the new course…

• 3 min read
Celsius Thermal Solver , SI , PI , PCB Signal and power integrity , Signal Integrity , PCB design , PowerDC

Verification

Various Types of Transaction-Based Interfaces (TLM) for DisplayPort VIP

Introduction Different RTL designs often require different specially designed parallel…

• 3 min read
Verification IP , uvm , VIP , DisplayPort , verification

Analog/Custom Design

Design Smarter: Unlock the Power of Virtuoso Auto Place and Route (APR)

Are you tired of sacrificing precious design time and risking errors with manual…

• 5 min read
Virtuoso Layout Suite MXL , Virtuoso Studio , Automated Device-Level Placement and Routing , Auto Place and Route , Automatic Placement , Auto P&R , Virtuoso Layout Suite EXL

Analog/Custom Design

Knowledge Booster Training Bytes: Design Checks and Asserts in Spectre Simulator

Let's quickly discuss design checks and asserts in the Spectre Simulator Platform…

• 3 min read
ADE Explorer , Virtuoso Analog Design Environment , Spectre , Custom IC Design , ADE Assembler

SoC and IP

Enkl Sound Elevates Audio Tech with Tensilica HiFi DSP for Unmatched Excellence

In the rapidly evolving world of audio technology, Enkl Sound Copenhagen emerges…

• 3 min read
Sound , Hearable , wearables , Tensilica HiFi DSP , Bluetooth Speakers

System, PCB, & Package Design 

Crafting Stellar Performance in the Rapidly Evolving Arm SoC Landscape

In an era where technology evolves at lightning speed, ensuring top-tier system performance…

• 4 min read
3D-IC , VIP , Cookbook , RAK , neoverse , ARM

Analog/Custom Design

From Concept to Reality: Understanding the Cadence Analog IC Design Flow

In this blog, you will explore the Analog IC design flow stages and highlight the…

• 6 min read
Pegasus Verification System , post-layout simulation , Analog Design Environment , GDSII , Virtuoso Studio , ADE Explorer , Analog Simulation , Auto P&R , Virtuoso Analog Design Environment , Spectre , Schematic Editor , Quantus Extraction Solution , iPegasus , Custom IC Design , Virtuoso Layout Suite , Parasitic extraction , ADE Assembler

Analog/Custom Design

Virtuoso Studio: Viewing Cross Section of a Layout

In your layout designs, use Cross Section Viewer to take a deeper look into a specific…

• 3 min read
featured , Virtuoso Studio

System, PCB, & Package Design 

Johanson Technology Adds Clarity Encryption Support to New Antenna Models

Johanson Technology has collaborated with Cadence to provide customers with encrypted…

• 2 min read
EM Analysis , antenna model , encrypted component , Johanson , component model , Clarity 3D Solver , 3D component

Life at Cadence

From Lands End to John o'Groats: Our Ride for Prostate Cancer UK

Written by Keith Tunstall, application engineer architect, and Kevin Donnelly, application…

• 4 min read
CadenceCares , giving back , Corporate Culture , charity , LifeAtCadence , life at cadence , volunteer

Corporate News

InspireSemi Is Paving the Way for the Next Generation of AI

InspireSemi's research indicates that high-performance compute (HPC), artificial…

• 2 min read
Tempus , designed with cadence , Quantus , Innovus Implementation

Digital Design

If You Don't See It, You Might Miss It!

The holiday week is here, and while this is a time for relaxing and re-energizing…

• 3 min read
digital design , DFT , online courses , LEC , RTL-to-GDSII , Digital Design Flow Videos , training bytes , Digital Implementation , implementation , RTL2GDSII , Synthesis , RTL design , Modus ATPG

Verification

Unraveling Orthogonal Header Content (OHC) in PCIe 6.0

Introduction With the arrival of Flit Mode, the information hold by the TLP header…

• 3 min read
System Design and Verification , VIP , PCIe , verification

Academic Network

Cadence Day at Texas A&M University

The Cadence Academic Network enthusiastically partners with universities to enhance…

• 3 min read
Cadence Day , featured , Cadence Academic Network , Texas A&M University , Industry-Academic Collaboration

PCB設計／ICパッケージ設計

2024年9月リリース、OrCAD X / Allegro X 24.1 の新機能ハイライト

OrCAD X / Allegro X 24.1が Cadence Downloads からダウンロード可能になりました。本ブログでは、このリリースにアクセスするための重要なリンクと…

• 1 min read
PCB , OrCAD X Capture CIS , new features , Allegro X PCB Editor , PSpiceA/D , Allegro X Advanced Package Designer , what's new , APD , PSPICE , Allegro Pulse , OrCAD X Presto , OrCAD X , 24.1 , japanese blog , allegro x , Allegro X System Capture

Computational Fluid Dynamics

Dual-Grid Interpolation: For Improved Accuracy of Overset Grid Systems

This blog post explores overset grid techniques, highlighting the challenges and…

• 4 min read
CFD , overset grid , simulation software , Meshing , Fidelity Pointwise

System, PCB, & Package Design 

Participating in Cadence Community Forums

Do you observe quietly or participate in online community discussions? If it’s the…

• 3 min read
PCB , CFD , Cadance Community Forums , Community , cadence , awr , Q&A , community forum , Cadence forums , PCB design

Verification

Introduction of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard

Universal Serial Bus (USB) technology is the most popular connector in every computing…

• 3 min read
eUSB2v2 , Functional Verification , VIP , USB , eUSB2

SoC and IP

Accelerate the Photonic IC Design with Cadence EPDA Environment

Do you believe the existing semiconductor methodologies will adequately support the…

• 4 min read
Photonic IC Design , EPDA Environment , photonics
CDNS - Fix Layout Hompage