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Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI
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Blog - Post List

Latest blogs

Breakfast Bytes

Palladium Z1, an Enterprise Server Farm in a Rack

If you put together your dream emulation system, it would have: Infinite throughput…

• 4 min read
virtualization , Enterprise , palladium z1 , Palladium , Emulation , simulation

Breakfast Bytes

I Danced with a Nun in a Disco…and the micro:bit

How's that for a click-bait title? But it's true. Back in 1969, the British government…

• 3 min read
BBC , microsoft , Acorn Computer , micro:bit , Open University , ARM , Breakfast Bytes

Breakfast Bytes

Ethernet: Coming Soon to a Car Near You

Ethernet was invented at the legendary Xerox PARC (Palo Alto Research Center) by…

• 5 min read
Automotive , can bus , MOST , ethernet phy , Ethernet , canbus , flexray

Breakfast Bytes

ARM's Mike Muller Announces a New Core, a New Instruction Set, and Security Laye…

Mike Muller, ARM's CTO, delivered a little history and a lot of security. Oh, and…

• 4 min read
security , ARM v8 , ARM Techcon , arm cortex-a35 , armv8-M , IoT , Muller , Internet of Things , ARM , Techcon

Whiteboard Wednesdays

Whiteboard Wednesdays - High-Speed QSPI Interface Challenges

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the challenges…

• less than a min read
Whiteboard Wednesdays , IP , QSPI interface , high-speed QSPI

Verification

Is There Market Appetite for PCIe 4.0? A View from Tokyo and Taipei

Coming back from the PCI-SIG Developer Conference Asia-Pacific Tour 2015 in Japan…

• 3 min read
PCIe Gen4 , VIP , PCIe , PCIe Gen3 , PCI-SIG

System, PCB, & Package Design 

What's Good About the DEHDL Variant Editor? The Secret's in the 16.6 Release!

The 16.6–2015 (also known as 16.6 QIR#9) Design Entry HDL (DEHDL) release contains…

• 9 min read
Cadence Design Systems , 16.6 , SPB , Design Entry HDL , Grzenia

Breakfast Bytes

How Did 3 Engineers Tape Out an ARM IoT Product in 3 Months?

The Internet of Things (IoT) is the hottest buzzword (buzzphrase?) in electronics…

• 4 min read
IoT , Internet of Things , ARM , reference platform

Life at Cadence

Cadence Is One of FORTUNE's Top 50 Best Workplaces for Diversity!

• less than a min read
World's Best , inclusion , Culture , cadence , GPTW , diversity , Fortune 100 best companies to work for , great place to work , best workplace for diversity

Life at Cadence

The Secrets to Building an Inclusive Culture

Many people ask me how Cadence has more than quadrupled its market cap over the last…

• 3 min read
World's Best , Insights on Culture , inclusion , Culture , cadence , Fortune , GPTW , diversity , great place to work , best workplace for diversity

Breakfast Bytes

Cadence Tool Suite Qualified for 22FDX Reference Flow

Let's pull a paragraph out of the joint Cadence/GF press release from earlier today…

• 4 min read
forward body bias , ARM Techcon , Global Foundries , expert bar , Tempus , 22fdx , 28nm , 20nm , arm cortex , rbb , reverse body bias , gf , Voltus , Innovus , FinFET , arm cortex-a17 , GlobalFoundries , ARM , quantus qrx , fbb , Techcon , FD-SOI

Breakfast Bytes

Where Does 5 Really Mean 30? Process Node Naming

In my first real blog here, about the Cadence/imec 5nm announcement, I asked what…

• 3 min read
Intel , process node , Samsung , TSMC , 5nm , GlobalFoundries , 7nm , 10nm , Breakfast Bytes

Breakfast Bytes

How Did Cadence Get to Be Good in Analog?

We recently held the annual Mixed Signal Technology Summit. I blogged about it and…

• 4 min read
cadence , diva , composer , analog , Virtuoso , analog mixed signal , OpenAccess

Whiteboard Wednesdays

Whiteboard Wednesdays—Automotive Functional Safety and Reliability Requirements

In this week’s Whiteboard Wednesday, Charles Qi talks about automotive functional…

• less than a min read
Automotive , Whiteboard Wednesdays , IP , functional safety , software , reliability

Breakfast Bytes

This Year's Phil Kaufman Award Recipient: Wally Rhines

This year's Phil Kaufman award recipient is Wally Rhines. I already knew the big…

• 4 min read
DSP , ti320 , Wally Rhines , walden rhines , Mentor Graphics , Kaufman Award , Texas Instruments , Breakfast Bytes , phil kaufman award , Mentor

Breakfast Bytes

The Phil Kaufman Award Dinner Is Later this Month. Who Was Phil Kaufman?

Every year one person in EDA is honored with the Phil Kaufman Award. As it says on…

• 4 min read
SCS , cadence , silicon compilers , sci , Quickturn , Phil Kaufman , Breakfast Bytes , phil kaufman award

Breakfast Bytes

Ten Years Ago Self-Driving Cars Couldn't Go Ten Miles

Recently Tesla activated Autopilot for their vehicles, which are equipped with the…

• 3 min read
delphi , darpa grand challenge , Stanford , autonomous vehicle , cmu , google , tesla , self-driving car , Breakfast Bytes

Breakfast Bytes

Mixed-Signal Symposium: Mixed Means More Digital

Earlier this week was the Cadence Mixed-Signal Technology Summit. Since I was the…

• 5 min read
Berkeley , analog , Mixed-Signal Technology Summit , mixed signal , analog mixed signal , Breakfast Bytes

System, PCB, & Package Design 

What's Good About Cadence PCB Design and SI/PI Analysis Products? The 16.6 release…

I’m taking a brief detour from the usual product technical details this week to mention…

• 2 min read
PCB , IC Packaging and SiP Design , Cadence Design Systems , SiP , Allegro 16.6 , Design Entry CIS , DEHDL , FPGA System Planner , High Speed , Allegro Design Workbench , PSPICE , SPB , PCB Editor , High-Density Interconnect , Constraint Manager , Design Entry HDL , Layout , OrCAD , PCB design , AMS simulation , Grzenia , Allegro PCB Editor , ConceptHDL , Allegro
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