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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects

Have you ever gotten to signoff DRC and found that there was a small area where a…

• 2 min read
power vias , filler cells , highlighted objects , checkFiller , 8.1 , Digital Implementation , verifyPowerVia , "SoC-Encounter" , F9

Verification

Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

Does the union of verification automation and IT+source code management tools get…

• less than a min read
DAC , Tivoli , metric driven verification (MDV) , Functional Verification , IBM , Enterprise Manager , Enterprise Planner , MDV , Rational , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Functional Verification and EDA "Startups"

A few weeks before DAC, I started working on a blog post about the number of small…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM , System Verification , verification

Analog/Custom Design

Things You Didn't Know About Virtuoso: RTFM

Wait, don't run away! In this case I really mean " Read The Fantastic Manual ". A…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Comment Direct From XJTAG, Ltd.

Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their…

• 2 min read
DAC , Functional Verification , XJTAG

Verification

Specman 9.2 Preview: Named Constraints

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 6 min read
IntelliGen , Specman , debug , Functional Verification , e , AOP , IES-XL

Verification

DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System…

One of the great things about DAC is the opportunity to meet new people and find…

• 2 min read
DAC , System Design and Verification , Incisive , SoC , Marvel

Verification

Survey Results and Commentary on The XJTAG Girls at DAC 2009

In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls…

• 7 min read
DAC , Functional Verification , OVM , XJTAG

System, PCB, & Package Design 

What's Good About Blogging? - The People: Readers, Posters, Cadence!

I'm taking a break this week from the technical type posts to say THANK YOU to the…

• 2 min read
IC Packaging and SiP Design , PCB design , FPGA

Verification

More Details on Post Silicon Embedded Software Verification With ISX

Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in…

• 3 min read
AXI , eVC , System Design and Verification , OVM , SoC , ISX , ARM , ESL , FPGA

Digital Design

Co-Design - Its Not Just an Exercise in Excel Any More - Learn Why at the Aug. 26…

Co-Design … some are trying to do it with spreadsheets … everyone is talking about…

• 1 min read
SoC-Encounter , Cadence SiP , Co-Design , Digital Implementation , FlipChip

Verification

Slides From DAC Virtual Platform Workshop

As a follow-up to my report on the DAC Virtual Platform Workshop I would like to…

• less than a min read
DAC , virtual platform , System Design and Verification

System, PCB, & Package Design 

What's Good About DEHDL Usability Improvements? The Secret's in the SPB16.2 Release

The Design Entry HDL (DEHDL) usability improvements are many and significant in the…

• 5 min read
SPB 16.2 , DEHDL , PCB design , Allegro

Digital Design

Useful dbGet One-Liners

We've gotten some good feedback about posts in this forum relating to dbGet and dbSet…

• 2 min read
dbGet , dbSet , Digital Implementation

System, PCB, & Package Design 

Power Issues? Manage Your IR Drop The "Advanced" Way

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written…

• less than a min read
16.01 , PCB Layout and routing , SPB 16.2 , PCB Signal and power integrity , Allegro 16.2 , SPB16.2 , PCB design

Verification

A Quick Look Back at DAC

Well, I had good intentions of blogging from DAC , or at least summarizing my four…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM

Analog/Custom Design

We Interrupt Your Regularly Scheduled Programming...

I thought I would have time for a regular TYDKAV (Things You Didn't Know About Virtuoso…

• 1 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital…

• 3 min read
RTL , System C , ESL , System Design and Verification

Verification

Full System vs Sub-system Virtual Prototyping

There is a strong movement in the industry to move to create Virtual Prototypes of…

• 2 min read
TLM , RTL , System Design and Verification , virtual prototype
CDNS - Fix Layout Hompage