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Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Constraint Layering - Fine Tuning Your Environment - Part 2

In my last post , I talked briefly about constraint layering in which I gave an extremely…

• 4 min read
IEEE 1647 , Specman , verification strategy , Verification methodology , Functional Verification , Testbench simulation , e , Aspect Oriented Programming , IES , AOP

Analog/Custom Design

Video Chat with Lead Architect of Virtuoso Accelerated Parallel Simulator

Virtuoso Accelerated Parallel Simulator was just released and I asked Ilya Yusim…

• 1 min read
mixed-signal simulators , MMSIM , Circuit Design , Simulators , Custom IC Design , custom design technology

Digital Design

Become an Encounter Digital Implementation System Specialist and Win Cool Prizes

Last week, we announced the Encounter Digital Implementation System along with a…

• less than a min read

Verification

New Technical Blog on e & Specman Technology

Specmaniacs of the world: rejoice! Members of Team Specman have just launched their…

• less than a min read
IEEE 1647 , Specman , e

Verification

Constraint layering - Fine Tuning Your Environment - Part 1

In today's environment of ever growing complexity and ever shrinking schedules,…

• 3 min read
IEEE 1647 , SystemVerilog , Specman , verification strategy , Verification methodology , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Verification

New e / Specman Workshops Available Now

In response to the continual growth in the e /Specman user community, Team Specman…

• 2 min read
workshops , IEEE 1647 , Specman , metric driven verification (MDV) , Functional Verification , Testbench simulation , MDV techtorial , OVM e , Coverage-Driven Verification , e , Kit , coverage driven verification (CDV) , eRM , IES

Verification

New Blog - All About e & Specman

End-users of e , Specman, Incisive Enterprise Simulator (IES), e RM/OVM e , and…

• 1 min read
IEEE 1647 , Specman , verification strategy , metric driven verification (MDV) , Functional Verification , Testbench simulation , OVM e , Coverage-Driven Verification , e , coverage driven verification (CDV) , eRM , Incisive Enterprise Simulator (IES) , IES

System, PCB, & Package Design 

What's Good About SPB16.2 OrCAD Capture? Many Usability Enhancements!

There are enormous usability updates in the SPB16.2 release of OrCAD Capture. From…

• 7 min read
SPB 16.2 , OrCAD , PCB design

Analog/Custom Design

What's New With Virtuoso?

If you were wondering what's new with Virtuoso you may want to check out the latest…

• less than a min read
MMSIM , Floorplanning , Virtuoso IC 6.1.3 , Virtuoso , RF design , Custom IC Design

Verification

Metric Driven System Level Verification

I have the great honor of introducing a wonderful paper on system level verification…

• 1 min read
System Design and Verification , ARC International , ISX

Verification

VMM Users -- Welcome to the OVM!

VMM users -- welcome to the OVM! We've been talking together about the benefits…

• 3 min read
SystemVerilog , Verification methodology , Functional Verification , OVM , VIP , e , eRM , OVMWorld

Digital Design

3 Reasons Why You Will Want to Download Encounter 8.1

Today is a big day in Digital Implementation land here at Cadence. Looking around…

• less than a min read
Flows , SoC-Encounter 8.1 , Low-Power , Digital Implementation , Floorplanning and Prototyping

System, PCB, & Package Design 

What's Good About the SPB16.2 Cross Referencer? Active Links in the Schematic!

That's right - an often requested feature from several customers has now been implemented…

• 2 min read
SPB 16.2 , PCB design

Digital Design

Innovate Your Way Out of Recession With the New Encounter!

It's official! The U.S. economy has been in a recession for the past year. …

• 2 min read
Static timing analysis , Early Rail Analysis , SoC-Encounter , Digital Implementation forums , First Encounter , SoC-Encounter 8.1 , Signoff Analysis , STA , encounter , Cadence Encounter Power System , Digital Implementation , CeltIC NDC , Global Timing Debug , Encounter Timing System , SSTA , Floorplanning and Prototyping , "SoC-Encounter"

Verification

News From the IP '08 Conference

My colleagues on the Verification IP team have been honored to present at the annual…

• 3 min read
HW/SW , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , VIP , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , Verification IP modeling , ISX

Digital Design

Demo: Using the Pin Editor in SoC-Encounter

SoC-Encounter has automatic partition pin assignment capabilites. The tool also…

• less than a min read
SoC-Encounter , partitioning , hierarchical design , Digital Implementation , Pin Editor

Verification

Follow-up on Posedge Software Interview

Just a quick follow-up to my previous interview with Henry Von Bank of Posedge Software…

• less than a min read
posedge , System Design and Verification , ISX

Verification

e Running Inside VCS Anniversary Updates?

It's been a year since I heard the first solid report about Synopsys supporting…

• less than a min read
IEEE 1647 , Specman , Testbench simulation , e , multi-language , Incisive Enterprise Simulator (IES) , IES

Digital Design

Tapeout!

With an early December tapeout looming, I've found myself too busy to write a post…

• 3 min read
ECO , LEC , DRC , LVS , Digital Implementation , Power Analysis , tapeout
CDNS - Fix Layout Hompage