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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

PCB、IC封装：设计与仿真分析

如何利用Virtuoso平台高效精确地设计一款射频前端模块电路（一）

作为一名射频前端设计的工程师，大家肯定都有过这样的疑惑：我究竟是做IC设计的，还是做板级电路设计的？如果是前者，为什么我们做仿真不跑corner，不跑蒙特卡罗，甚至连个精确的晶体管模型都没有…

• less than a min read
射频 , Chinese blog , 仿真分析 , 射频前端模块 , 协同仿真 , Virtuoso , 中文

Breakfast Bytes

Brad Brim and the History of Signal Integrity

I sat down with Brad Brim recently. He was retiring from Cadence literally the following…

• 6 min read
system analysis , Signal Integrity , Sigrity , clarity

System, PCB, & Package Design 

Power Plane Loop Inductance Guidance for PDN Designers

Gaining an understanding of power plane loop inductance is important for efficient…

• 1 min read
SI , DesignCon , PDN , Power plane loop inductance , DesignCon 2019 , Signal Integrity , Sigrity , PowerSI

Analog/Custom Design

Virtuoso Video Diary: Creating and Previewing Stimuli

If you've ever tried to add stimuli to your design using the Stimuli form, you'll…

• 3 min read
ADE Explorer , stimuli form , stimuli , Virtuoso Analog Design Environment , ViVA , Virtuosity , ADE Blog Series , Custom IC Design , ADE Assembler , Stimuli Assignment form

Breakfast Bytes

Superhuman Photonic Design

I recently came across an article titled Generative Design Could Radically Transform…

• 3 min read
curvycore , Lumerical , silicon photonics , Virtuoso , photonics

Breakfast Bytes

TI's Experience Taping out with Pegasus

At the recent CDNLive Silicon Valley, Kyle Peavy of Texas Instruments (TI) presented…

• 5 min read
CDNLive , pegasus , DRC , design rule check , CDNLive Silicon Valley

Analog/Custom Design

Virtuoso Video Diary: Tune In to the MPT Video Channel

Tune In to the MPT Video Channel to check out a wide range of features easily accessible…

• 1 min read
ICADVM18.1 , video , Layout , Virtuoso , Virtuoso Video Diary , advanced nodes , multi-patterning technology , Custom IC

Whiteboard Wednesdays

Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual…

In this week's Whiteboard Wednesdays video, Senior Product Engineering Manager Varun…

• less than a min read
Whiteboard Wednesdays , Quantus , IVMF

Breakfast Bytes

Barefoot in a CloudBurst: Tempus on 2000+ CPUs

Barefoot Networks gave a couple of presentations at the recent CDNLive Silicon Valley…

• 5 min read
CDNLive , barefoot networks , cloudburst , cadence cloud , CDNLive Silicon Valley

Breakfast Bytes

Driving Dangerously

I've written a few times before about the fragility of neural networks, for example…

• 5 min read
Automotive , deep learning , tesla , ADAS , neural networks

Breakfast Bytes

Sunday Brunch Video for 7th April 2019

https://youtu.be/DUu3M30lilE Made at CDNLive Silicon Valley (camera Sean) Monday…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

Chiplets——重新定义系统设计

当下，电子行业经历着系统设计的新范式转变：传统的单片SoC电子系统设计思路正逐渐转变为使用chiplets（即“小芯片”）和高级封装技术的多芯片设计方法。这种逆转思维为系统设计开启了一个新的时代…

• less than a min read
SI , PI , Chinese blog , 电源完整性 , chiplets , 异质集成 , 中介层提取 , 系统设计 , IC封装设计 , 多芯片设计 , 高级封装 , 基于chiplets的系统 , 中文 , Sigrity , 信号完整性

The India Circuit

Simple Things You Can Do To Get Ahead In The Workplace

Recently we were lucky to have two of the women vice presidents at Cadence – Karna…

• 3 min read
International Women's Day , Women at Cadence , Cadence India , women leaders

Breakfast Bytes

RSA: Public Interest Technologists

Yesterday, I wrote about the first half of Bruce Schneier's keynote at the recent…

• 7 min read
security , policy , schneier

Analog/Custom Design

Virtuoso Video Diary: Checking EM Compliance Before Creating Layouts

How about checking your designs for electromigration (EM) compliance before creating…

• 2 min read
EAD , electromigration , ICADVM18.1 , electrically-aware design flow , Virtuoso electrically-aware design flow , EM , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

RSA: Bruce Schneier

I have been following Bruce Schneier for a long time. He literally wrote the book…

• 5 min read
security , public interest technology , rsa , schneier

Academic Network

Best Paper Award at LATS2019 for Zhan Gao

The IEEE Latin-American Test Symposium (LATS) is an annual forum attended by professionals…

• 2 min read
Cadence Academic Network , academia , CDNLive EMEA , modus , imec

System, PCB, & Package Design 

BoardSurfers: Validating Your Shapes

Your design is near completion. Except that you’ve got an area of your plane shape…

• 5 min read
PCB Editor , PCB design and layout , Shape Checks , Allegro

Breakfast Bytes

Geoff Hinton, Yann LeCun, and Yoshua Bengio Win 2019 Turing Award

This year's Alan Turing Award goes to Geoff Hinton, Yann LeCun, and Yoshua Bengio…

• 4 min read
deep learning , turing award , neural networks , AI
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