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Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 27 Aug 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
Corporate 21 Aug 2025 • 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
Vinod Khera 31 Jul 2025 • 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 23 Jul 2025 • 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

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Blog - Post List

Latest blogs

PCB、IC封装:设计与仿真分析

针对电气工程师的热管理基础——第一篇

作者:Lawrence Der 在过去,机械工程师全权负责产品的热力设计,包括产品的机械外壳和其它物理方面的设计;然而现在,热力设计问题却是要电气工程师来共同承担…

Sigrity 9 Nov 2018 • less than a min read
热 , Chinese blog , 热分析 , 温度 , 中文 , PowerDC , 传热 , 热基础

Breakfast Bytes

Kaufman Award Dinner: The Tom Williams Story

Wednesday night it was the annual Kaufman Award Dinner to honor this year's recipient…

Paul McLellan 9 Nov 2018 • 6 min read
kaufman dinner , scan , Scan test , IBM , Kaufman Award , tom williams , lssd , synopsys

Breakfast Bytes

RISC-V Summit Preview: Pascal or Linux?

Coming up in December, in the same week as IEDM, is the RISC-V Summit at the Santa…

Paul McLellan 8 Nov 2018 • 3 min read
risc-v , Spectre , instruction set architecture

Breakfast Bytes

IEDM Preview: 3nm and More

A lot of aspects of EDA and semiconductor are fairly easy to predict: you read off…

Paul McLellan 7 Nov 2018 • 5 min read
IBM , 3nm , Samsung , imec , gaa , tu dresden , IEEE , IEDM

Whiteboard Wednesdays

Whiteboard Wednesdays - How the Cadence 112G SerDes IP Solves the Challenges of Long…

In this week’s Whiteboard Wednesday, Wendy Wu explains what NRZ and PAM-4 signaling…

References4U 6 Nov 2018 • less than a min read
Whiteboard Wednesdays , 100G Ethernet , 112G SerDes , PAM-4 , SerDes , 400G Ethernet , 800G Ethernet

Breakfast Bytes

Automotive Summit: Driving an Industry with Electronics

Coming up on November 14th is the Cadence Automotive Summit. This will be held on…

Paul McLellan 6 Nov 2018 • 3 min read
Automotive , lidar , radar , Tensilica , vision , ISO 26262 , ADAS , ARM

The India Circuit

A Diwali with Green Crackers and Cooking Bots

It’s Diwali! My favorite festival out of all the many celebrations that we Indians…

Madhavi Rao 5 Nov 2018 • 3 min read
firecrackers , green cracker , air pollution , Diwali

Breakfast Bytes

Breakfast Buffet for October 2018

https://youtu.be/YBlBzB3n504 The three highlighted posts for October were: CDNLive…

Paul McLellan 5 Nov 2018 • less than a min read
hifi 5 , breakfast buffet , 112G SerDes , cdnlive israel

Breakfast Bytes

China Update

Over the last couple of weeks, I came across various little things about China, none…

Paul McLellan 5 Nov 2018 • 6 min read
China , Micron , semi , DRAM , ic insights , bloomberg

Breakfast Bytes

Sunday Brunch Video for 4th November 2018

https://youtu.be/HCJG-tABZWE Made at Linley Fall Processor Conference (camera Sean…

Paul McLellan 4 Nov 2018 • less than a min read
Automotive , hifi 5 , curvycore , formal , openroad , Tensilica , photonics , Texas Instruments , JasperGold , darpa

PCB、IC封装:设计与仿真分析

升级到Allegro17.2-2016的10大理由之10:易于使用的改进

我所认识的大多数PCB设计工程师跟我有同样的习惯… 我们有最喜欢的颜色、板层名称、定制的键盘,我们最大的目标是看到一天之内完成了多少条网络布线。我们很少有改变这些使用习惯…

TeamAllegro 2 Nov 2018 • 1 min read
PCB , Chinese blog , Allegro 17.2 , PCB设计 , 中文 , Allegro PCB Editor , Allegro PCB编辑器 , Allegro升级17.2 , Allegro

Breakfast Bytes

ERI: OpenROAD

If I had to summarize DARPA's Electronic Resurgence Initiative in one phrase, it…

Paul McLellan 2 Nov 2018 • 6 min read
openroad , kahng , open source , eri , darpa

Breakfast Bytes

Yoga is Passé, the Future Is CurvyCore

Despite CurvyCore sounding like something that you might take classes in at your…

Paul McLellan 1 Nov 2018 • 5 min read
curvycore , conformal routing , Virtuoso , photonics

Breakfast Bytes

"Alexa, What Is HiFi 5?"

"Alexa, turn on the living room light." "Okay." "Alexa, what is Cadence announcing…

Paul McLellan 31 Oct 2018 • 4 min read
hifi 5 , alexa , audio , voice recogntion , Tensilica

Whiteboard Wednesdays

Whiteboard Wednesdays – Machines with Voice UI and Tensilica HiFi 5 DSP

In this week’s Whiteboard Wednesdays video, Sachin Ghanekar talks about the new Tensilica…

References4U 31 Oct 2018 • less than a min read
Whiteboard Wednesdays , HiFi DSP , neural networks

Analog/Custom Design

Virtuosity: Is the Coloring Data Compliant with the MPT Flow?

In advanced node designs, to help you create designs that are compliant with the…

KomalJohar 31 Oct 2018 • 2 min read
Advanced Node , Multiple Patterning Technology , Virtuoso , Coloring Engine , Custom IC , Layout Editing

System, PCB, & Package Design 

How Do I Know What Functionality to Put on Which PCB Board?

There’s only so much you can do with a single printed circuit board (PCB). We’ve…

TeamAllegro 30 Oct 2018 • 4 min read
PCB , multi-board systems , multiboard PCB , PCB design , multiboard systems , Multi-board PCB , Allegro

Breakfast Bytes

Texas Instruments on Automotive Reliability

Recently, I seem to have been running into people from Texas Instruments (TI) talking…

Paul McLellan 30 Oct 2018 • 8 min read
Automotive , electromigration , functional safety , aging , Texas Instruments , fusa , reliability

Breakfast Bytes

Formal Signoff with JasperGold

At the recent Jasper User Group, I said that there were several themes. For overall…

Paul McLellan 29 Oct 2018 • 5 min read
Jasper User Group , JUG , formal , signoff , JasperGold
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