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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview February 20th to 24th 2017

https://youtu.be/EVZ4T8TPim8 Coming from inside a Microsoft Hololens Monday…

• less than a min read
holoens , DesignCon , spie advanced lithography , Mobile World Congress , MWC , rocketsim , target impedance , parallel simulation

Analog/Custom Design

Virtuoso Video Diary: Eye Masks

Have you ever plotted an eye diagram in Virtuoso Visualization and Analysis XL and…

• 4 min read
Eye Mask , Analog Design Environment , Eye , ADE GXL , ViVa-XL , ADE Explorer , Analog Simulation , ADE XL , ADE , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuoso Video Diary

Breakfast Bytes

The Second Embedded Neural Network Symposium

A couple of weeks ago, Cadence held the second embedded neural network symposium…

• 8 min read
deep neural networks , enns , dnn , embedded neural networks , neural networks

Breakfast Bytes

Integrated Bus Routing Solution

For most chips, the automatic routing in Innovus—NanoRoute—works well. But there…

• 3 min read
integrated bus routing solution , grid-based routing , analog , Innovus , high frequency router

Breakfast Bytes

Circuits and Systems for Security and Privacy

One of the perks of writing this blog is that I get offered review copies of interesting…

• 6 min read
security , side channel attacks , encryption , puf , crc press , random number , physically unclonable functions

Breakfast Bytes

Tom Quan on TSMC's Automotive Strategy

Tom Quan recently came to Cadence to talk about TSMC's automotive strategy. Tom and…

• 4 min read
Automotive , tom quan , TSMC , 7ff , 16FFC , ISO 26262 , ADAS , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview February 13th to 17th 2017

https://youtu.be/HL0GFG9tNP4 Coming from Cadence security camera Monday…

• less than a min read
deep learning , machine learning , convolutional neural networks , moore's law , embedded neural networks , neural networks , machine vision

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplify UVM Scoreboarding with Cadence VIP

In this week's Whiteboard Wednesdays video, principal AE Matt Diehl explains how…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , DisplayPort , Matt Diehl

Breakfast Bytes

He Who Goes First Loses, EDA Edition

Yesterday I wrote a post He Who Goes First...Loses about how being first isn't always…

• 4 min read
point tools , hunters , EDA , ambit , farmers

Breakfast Bytes

He Who Goes First...Loses

There is a saying, of course, that he who goes first wins. And sometimes, and in…

• 5 min read
apple pay , credit cards , m-pesa , tube , london tube

Breakfast Bytes

Handling Variability in the Modern Design Cycle

Igor Keller gave an internal presentation on Handling Variability in the Modern Design…

• 6 min read
on chip variation , AOCV , STA , OCV , variability , voltage droop , static timing , layout dependent effects , miller capacitance , SOCV , crosstalk , slew , SSTA

Verification

Preview of an Exciting DVCon

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest…

• 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Breakfast Bytes

What's For Breakfast? Video Preview February 6th to 10th 2017

https://youtu.be/XOS4sfILahc Coming from Design Con 2017 Monday: He Who…

• less than a min read
security , Automotive , Routing , TSMC , business strategy , Innovus , privacy

Verification

IEEE Std 1647™ 2016 - e Language - New Standard Publication

Congratulations to the IEEE-1647 e Functional Verification Language Working Group…

• 2 min read
IEEE 1647 , Specman , e , e language , specman elite

Breakfast Bytes

The ASML Standard Node

One of the first posts I wrote here at Breakfast Bytes was Where Does 5 Really Mean…

• 3 min read
mmhp , cphp , standard node , EUV

Breakfast Bytes

The Book for Practicing Formal Verification Engineers

At the no-longer-so-recent Jasper User Group JUG last year, the keynote was by Erik…

• 3 min read
formal verification book , Formal verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Ethernet: Not Your Grandfather's Ethernet

In this week's Whiteboard Wednesdays, Scott Jacobson wraps up his three-part series…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , Automotive Ethernet , Ethernet

Breakfast Bytes

ENIAC, EDSAC and Colossus... and the Difference Engine

There are lots of claims to be the first computer, depending on your definition of…

• 5 min read
edsac , analytical engine , mercury delay line , difference engine , first stored program computer , eniac

Analog/Custom Design

Virtuoso Video Diary: Is It That Easy to Edit in the Virtuoso Schematic Editor?

Creating a neat and organized schematic is extremely important, and often requires…

• 3 min read
Virtuoso Schematic Editor , VSE L , Advanced Node , VSE XL , Virtuoso Video Diary , Custom IC Design
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