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Featured

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
Cadence Japan 15 Dec 2025 • less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
Corporate 11 Dec 2025 • 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP(Verification IP:VIP)を発表しました。今回発表されたVIPは…

Cadence Japan
Cadence Japan 4 Dec 2025 • less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
Cadence Japan 1 Dec 2025 • 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview May 15th to 19th 2017

https://youtu.be/WTQhUyl2BBE Coming from Jing'an Park, Shanghai, China (camera…

Paul McLellan 10 May 2017 • less than a min read
Automotive , dreamchip , CDNLive , CDNLive Munich , Tensilica , software development

Breakfast Bytes

Are General-Purpose Microprocessors Over?

There is apparently a rule of thumb among journalists that when the headline of an…

Paul McLellan 10 May 2017 • 8 min read
Intel , risc-v , processor , MIPS , Tensilica , RISC , ARM , microprocessor , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - CNN Challenges: Compute Requirement

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into compute…

References4U 9 May 2017 • less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Soft Error Rates in Satellites and Cars

Space turns out to be an interesting area for semiconductors, especially looking…

Paul McLellan 9 May 2017 • 8 min read
Automotive , st microoelectronics , ser , soft error rate , cubesat , see , single event effect , seu , space , Breakfast Bytes , satellite

Breakfast Bytes

NASA: "Never Have Another Accident Due to Our Organizational Flaws"

The keynote at the IRPS reliability conference I attended was by Nancy Currie-Gregg…

Paul McLellan 8 May 2017 • 7 min read
space shuttle , NASA , Breakfast Bytes , reliability

Breakfast Bytes

TSMC @ N7 with Cadence

One presentation at the recent CDNLive Silicon Valley was about using Cadence tools…

Paul McLellan 5 May 2017 • 4 min read
Genus , Tempus , TSMC , n7 , Innovus , Quantus , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: How Can I Plot or Evaluate with the New Expression Builder…

Indeed, the new Expression Builder has made expression creation much easier, but…

Arja H 5 May 2017 • 3 min read
Analog Design Environment , evaluateADE Explorer , Analog Simulation , plot , expressions , analog , Mixed-Signal , Expression Builder , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design , calculator

Breakfast Bytes

UVM Is Now IEEE 1800.2 and There's a Ten-Year Story to That

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered…

Paul McLellan 4 May 2017 • 6 min read
SystemVerilog , Superlog , ieee 1800.2 , uvm , Accellera , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 8th to 12th 2017

https://youtu.be/sIFo4JKjVxw Coming from NASA Ames Research Center, Sunnyvale…

Paul McLellan 3 May 2017 • less than a min read
space shuttle , risc-v , NXP , ser , 22fdx , soft error rate , 12fdx , Samsung , single event upset , Tensilica , single event effect , ST Microelectronics , GlobalFoundries , ARM , microprocessor , NASA , reliability , FD-SOI

Breakfast Bytes

Bayern München Will Not Be at CDNLive Munich: Here's What They Will Miss

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern…

Paul McLellan 3 May 2017 • 3 min read
Automotive , NXP , Munich , CDNLive , CDNLive EMEA , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays – Introduction to Cadence Tensilica Vision C5 DSP

In this week's Whiteboard Wednesdays video, Pulin Desai describes the main features…

References4U 2 May 2017 • less than a min read
Whiteboard Wednesdays , Vision DSP , convolutional neural networks , CNN

Breakfast Bytes

Test Flying Pegasus

Scott Barric of MicroSemi is one of the people who have been using the pre-release…

Paul McLellan 2 May 2017 • 5 min read
Physical verification , pegasus , DRC , cloud , microsemi , design rule check , PVS , Breakfast Bytes , cloud computing

Digital Design

Designing for Low Power… Begin at the Beginning

So you have your RTL written, and it’s time to optimize to reduce power. If that…

dpursley 1 May 2017 • 3 min read
Low Power , high level synthesis , power , HLS

Analog/Custom Design

Virtuosity: The Reboot

It’s been quite a while since I wrote about “Things I Learned by Browsing Cadence…

Arja H 1 May 2017 • 2 min read
Analog Design Environment , ADE GXL , ADE Explorer , Rapid Adoption Kit , Analog Simulation , ADE XL , ADE , ADE-GXL , Analog Design Environment , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Breakfast Bytes

Vision C5 DSP for Standalone Neural Network Processing

I pointed out recently that although La La Land is a romance, the movie opens with…

Paul McLellan 1 May 2017 • 6 min read
DSP , Vision C5 , embedded vision , Embedded Vision Alliance , Tensilica , semiconductor IP , embedded vision conference , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 1

In this week's Whiteboard Wednesdays video, Tom Hackett traces the evolution of the…

References4U 28 Apr 2017 • less than a min read
Whiteboard Wednesdays , ccix

Breakfast Bytes

Growth Comes from Solving New Problems—ESD Alliance CEO Panel

First, some sad news. Bob Gardner, for many years the executive director of the ESD…

Paul McLellan 28 Apr 2017 • 12 min read
cadence , EDAC , arm holdings , ARM , synopsys , Breakfast Bytes , esd alliance , Mentor

Breakfast Bytes

Microsoft CDNLive Keynote: Cloudy with a Chance of Chips

Traditionally at CDNLive Silicon Valley, the first keynote is given by Lip-Bu Tan…

Paul McLellan 27 Apr 2017 • 7 min read
microsoft , deep learning , cloud , azure , CDNLive Silicon Valley , Breakfast Bytes

Breakfast Bytes

The IRDS Panel at IRPS

Confused by those names? The conference is the International Reliability and Physics…

Paul McLellan 26 Apr 2017 • 4 min read
irds , ITRS , international roadmap for devices and systems , irps , IEEE , Breakfast Bytes , rebooting computing
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