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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment V22.1 ソフトウェアのリリースをハイライト

The Cadence AWR Design Environment V22.1 production release is now available for…

• 2 min read
RF , RF Simulation , AWR Analyst , Circuit simulation , AWR Design Environment , awr , EDA , AWR AXIEM , RF design , Circuit Design , AWR V22.1 release , microwave office , japanese blog , Visual System Simulator(VSS)

Breakfast Bytes

TSMC OIP: N3E/N4P, 3DFabric, Analog Migration

Today, it ia TSMC's OIP, the Open Innovation Platform Ecosystem Forum. I will write…

• 4 min read
OIP , RF , mmwave , n3e , TSMC , n4p , n16

RF Engineering

μWaveRiders: Cadence AWR Design Environment V22.1 Software Release Highlights

The Cadence AWR Design Environment V22.1 production release is now available for…

• 5 min read
RF , RF Simulation , AWR Analyst , Circuit simulation , AWR Design Environment , awr , EDA , AWR AXIEM , RF design , Circuit Design , AWR V22.1 release , microwave office , Visual System Simulator (VSS)

Computational Fluid Dynamics

On-Demand Webinar - Reduce Ship Fuel Emissions and Costs Through CFD Optimizatio…

Ship designs, made in CAD software, are becoming more complex every day, and CFD…

• less than a min read
CFD , naval archicture , Marine Engineering , shipping , greenhouse gases , FINE Marine , marine design , marine , fine/marine , Computational Fluid Dynamics , sustainability

Computational Fluid Dynamics

Women in CFD with Shi Yee Lim

The Women in CFD series highlights the career expedition of women in computational…

• 5 min read
CFD , product engineer , fluid dynamics , WomenAtCadence , Fidelity CFD , women in engineering , engineering , simulation software , NUMECA , Women in CFD

Cloud

For Advanced Chip Design, It’s Time To Go Cloud-First

EDA in the cloud is on the cusp of mass adoption. Semiconductor companies big and…

• 6 min read
SaaS , featured , cloud

Breakfast Bytes

Jasper User Group 2022: Ziyad's SOTU

This year's Jasper User Group meeting took place last week. As usual, the meeting…

• 3 min read
Jasper User Group , featured , JUG , formal , jjasper , Formal verification

Verification

DisplayPort (DP) Tunneling over USB4

USB4 is an industry standard that tunnels three different protocol specifications…

• 2 min read
Verification IP , USB4 VIP , USB4v2 , USB4 DP Tunneling , DP Tunneling , usb4

Computational Fluid Dynamics

Last Week at Fidelity CFD

Good morning and welcome to the last full week of October. Before we plunge into…

• 4 min read
Marine Engineering , automotive engineering , FINE Marine , turbulence , geometry cleanup , overset meshing , RANS , solar vehicles , Pointwise , cadencelive , scale-resolving simulation , Mesh Generation

Breakfast Bytes

IEDM and RISC-V Summit 2022 Previews

There are two big events coming up in the first couple of weeks of December. IEDM…

• 5 min read
risc-v , risc-v summit , IEDM

Verification

Demystifying PCIe Lane Margining Technology

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology…

• 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification

Breakfast Bytes

Cadence, McLaren, and the United States (Austin) Grand Prix

As you probably know, Cadence has a technology partnership with McLaren racing. I…

• 5 min read
CFD , F1 , mclaren , formula 1

Life at Cadence

Building Confidence through the Cadence Returnship Program

Re-entering the high-tech field after taking a break to prioritize family can be…

• 1 min read
Cadence Culture , returnship

System, PCB, & Package Design 

Cadence OrCAD and Allegro 22.1 is Now Available

The OrCAD® and Allegro® 22.1 release is now available at Cadence Downloads . This…

• 6 min read
TopXp , Cadence Design Systems , Sigrity Aurora , PSpiceA/D , 22.1 , PSPICE , Topology Explorer , PCB design , Allegro System Capture , Allegro PCB Editor , Pulse , Allegro

Life at Cadence

IQM Is Building the Next Generation of Quantum Computers

IQM seeks to solve one of the greatest technological challenges globally: building…

• 1 min read
RF , awr , designed with cadence

Life at Cadence

RISC-V Is Thriving – Here’s What You Need to Know

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley…

• 4 min read
risc-v

Breakfast Bytes

Latinx Heritage Month

Last week, Cadence held a Mercado Fiesta on the campus to celebrate Latinx Heritage…

• 2 min read
latinx , latinx heritage month , Hispanic

Analog/Custom Design

Start Your Engines: Clone your AMS Designer Testcases and Rerun them Anywhere

Design Capture and Packaging (DCP) utility lets you isolate, capture and package…

• 5 min read
mixed signal design , AMS Designer , AMSD , Start Your Engines , Mixed-Signal , Design Capture , Cadence Community

Digital Design

HLS for AI/ML Models: TensorFlow to RTL

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging…

• 3 min read
Stratus HLS , Genus
CDNS - Fix Layout Hompage